Split-Gate Memory Cell Layout With Recessed Substrate Height Control
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Solution Overview
Problem
Conventional split gate non-volatile memory cells have a greater height on the substrate compared to logic and high voltage devices, making it challenging to reduce their height while maintaining performance.
Innovation Solution
The method involves forming split gate non-volatile memory devices on a semiconductor substrate with recessed areas for memory cells, using metal or polysilicon control gates and high K dielectric materials, and independently adjusting the thickness of oxide layers to achieve co-planar top surfaces with logic and high voltage devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional split gate memory cells are formed with standard height, then manufacturing process is simpler, but the memory cell height becomes greater than logic and high voltage devices
Solution Approach 1:
The patent introduces a vertical dimension adjustment by forming a recess in the substrate specifically for the memory cell region. This recess allows the memory cell structure to be embedded deeper into the substrate, reducing the overall height of the memory cell stack relative to the substrate surface, while logic and high voltage devices maintain their standard height on the unrecessed substrate surface.
Solution Approach 2:
The patent applies local quality by creating a recessed region specifically for memory cells while leaving other regions (logic and high voltage device areas) at the standard substrate level. This localized structural modification allows different device types to have different optimal heights without requiring global process changes.
2Length of stationary object
If memory cell height is reduced to match logic devices, then co-planar top surfaces are achieved, but masking steps increase to prevent contamination
Solution Approach 1:
The patent segments the substrate into distinct regions with different heights: a recessed region for memory cells and an unrecessed region for logic and high voltage devices. This segmentation is achieved through region-specific etching processes that create isolated recesses, allowing independent height control for different device types.
Solution Approach 2:
The recess structure acts as an intermediary element that mediates between the conflicting requirements of memory cell height reduction and contamination prevention. By providing a physical depth barrier through the recess, the design reduces the need for extensive masking steps while maintaining co-planar top surfaces.
3Length of stationary object
If recessed areas are formed for memory cells, then memory cell height is reduced, but substrate processing complexity increases
Solution Approach 1:
The recess formation is performed as a preliminary action before forming the memory cell structures. By pre-configuring the substrate topography with the recess, subsequent memory cell formation processes can proceed with standard deposition and patterning techniques, avoiding the need for complex in-situ height control during memory cell fabrication.
Data Source
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AI summary
A memory device includes a memory cell, a logic device and a high voltage device formed on the same semiconductor substrate. Portions of the upper surface of the substrate under the memory cell and the high voltage device are recessed relative to the upper surface portion of the substrate under the logic device. The memory cell includes a polysilicon floating gate disposed over a first portion of a channel region of the substrate, a polysilicon word line gate disposed over a second portion of the channel region, a polysilicon erase gate disposed over a source region of the substrate, and a metal control gate disposed over the floating gate and insulated from the floating gate by a composite insulation layer that includes a high-K dielectric. The logic device includes a metal gate disposed over the substrate. The high voltage device includes a polysilicon gate disposed over the substrate.