Split-Gate RRAM Architecture for Endurance and Yield
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Solution Overview
Problem
Resistive random-access memory (RRAM) devices based on amorphous silicon (a-Si) structures face endurance issues due to excessive bias voltage during write and erase cycles, leading to shortened device life and yield problems during the electroforming process.
Innovation Solution
A memory array architecture incorporating a-Si based two-terminal memory cells with a switching medium between electrodes, utilizing program and erase transistors, and select transistors to control voltage applications, allowing for controlled formation and retrieval of conductive filaments to manage resistance states without excessive ion movement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If excessive bias voltage is applied during write and erase cycles, then resistance switching is achieved, but device endurance is shortened
Solution Approach 1:
The patent implements dynamic voltage distribution through a split-gate transistor architecture where the first gate controls channel formation and the second gate controls carrier injection. This dynamic separation allows precise control of voltage application, enabling resistance switching at lower overall bias voltages while maintaining reliability.
Solution Approach 2:
The patent changes the electrical parameters by introducing a dual-gate configuration that independently controls threshold voltage and channel conductivity. This parameter control mechanism enables switching operations at reduced voltage levels, directly addressing the endurance issue caused by excessive bias voltage.
2Reliability
If high voltage is applied during electroforming process, then conducting path is formed, but device yield is affected
Solution Approach 1:
The patent applies preliminary low-voltage channel formation through the first gate before applying the forming voltage through the second gate. This preliminary action prepares the conductive path gradually, reducing the stress of high voltage application and improving device yield during the electroforming process.
Solution Approach 2:
The dual-gate transistor enables dynamic control of the electroforming process by sequentially activating gates. The first gate establishes initial conduction, then the second gate completes the forming process at controlled voltage levels, preventing yield degradation from excessive voltage stress.
3Reliability
If metal ions move in a-Si structure, then conductive filaments are formed, but Joule heating occurs
Solution Approach 1:
The patent creates local control of ion migration and filament formation through the second gate, which is coupled to the a-Si layer. This localized control confines the resistive switching action to specific regions, reducing overall Joule heating while maintaining effective resistance switching through controlled metal ion movement in the a-Si structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the endurance and yield of RRAM devices by maintaining resistance states effectively, preventing sneak-path currents and allowing for diode-like behavior, thus improving the reliability and density of memory storage.
Implementation Method 1
The resistance switching has been explained by the formation of conductive filaments inside the insulator layer due to Joule heating and electrochemical processes
Implementation Method 2
The resistance switching has been explained by the formation of conductive filaments inside the insulator layer due to Joule heating and electrochemical processes in binary oxides
Implementation Method 3
In the case of a-Si structures, electric field-induced diffusion of metal ions into the silicon leads to the formation of conductive filaments that reduce the resistance of the a-Si structure
Implementation Method 4
These filaments remain after a biasing (or program) voltage is removed, thereby giving the device its non-volatile characteristic
Implementation Method 5
they can be removed by reverse flow of the ions back toward the metal electrode under the motive force of a reverse polarity applied voltage
Data Source
AI summary
A non-volatile memory device includes a word line extending along a first direction; a bit line extending along a second direction; a memory unit having a read transistor coupled to the bit line, at least one two-terminal memory cell, and a select transistor, the two-terminal memory cell having a first end coupled to the word line and a second end coupled to a gate of the read transistor. The second end of the two-terminal memory cell is coupled to a common node shared by a drain of the select transistor and the gate of the read transistor.