Split-Gate Semiconductor Device with Segmented Select Gate Electrode
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Solution Overview
Problem
The miniaturization of semiconductor devices with non-volatile memories faces challenges in manufacturing yield, reliability, and performance due to issues with charge storage layers and alignment margins in photolithography, leading to problems such as charge leakage and shape failures in contact holes.
Innovation Solution
A semiconductor device with a split-gate structure featuring a memory gate electrode in a sidewall shape and a pad electrode formed over a select gate electrode, where the pad electrode is connected to the memory gate electrode, allowing for reduced interlayer insulating film thickness and improved contact hole formation, thereby enhancing manufacturing yield and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the interlayer insulating film is made thinner to advance miniaturization, then device density and integration are improved, but contact hole formation becomes more difficult leading to shape failures and high resistance
Solution Approach 1:
The patent introduces a feeding region that extends the select gate electrode in the channel length direction, creating a three-dimensional structure that allows pad electrodes to be formed on the sidewalls. This dimensional change enables contact holes to be formed at optimized positions and depths, resolving the manufacturing difficulty caused by thin interlayer insulating films while maintaining high device density.
Solution Approach 2:
The select gate electrode is segmented into a memory cell region and a feeding region with different heights. The feeding region extends lower than the memory cell region, creating distinct zones that allow separate optimization of contact hole formation and memory cell operation. This segmentation enables contact holes to be formed in the feeding region without compromising the integrity of the thin interlayer insulating film in the memory cell region.
2Length of moving object
If photolithography alignment margin is reduced to advance miniaturization, then device dimensions are improved, but charge leakage and shape failures occur due to misalignment
Solution Approach 1:
The patent utilizes the channel length direction (third dimension in the planar layout) to extend the select gate electrode into a feeding region. This allows the memory gate electrode to be positioned with adequate alignment margin relative to the extended select gate, preventing charge leakage while maintaining miniaturized device dimensions in the critical width directions.
Solution Approach 2:
The feeding region acts as an intermediary structure that mediates between the memory gate electrode and the select gate electrode. By extending the select gate into this intermediate zone, the patent provides a buffer that accommodates photolithography alignment variations without causing charge leakage or shape failures in the functional memory cell region.
3Manufacturing precision
If contact hole depth and diameter are reduced to improve manufacturing yield, then contact resistance is improved, but shape failures and high resistance occur
Solution Approach 1:
The patent performs preliminary action by extending the select gate electrode into the feeding region before forming contact holes. This pre-positioning creates an optimized contact hole formation zone with appropriate depth and diameter characteristics, ensuring reliable electrical connection without shape failures. The feeding region is prepared in advance to accommodate contact hole formation at optimal dimensions.
Solution Approach 2:
The patent applies local quality by creating a feeding region with distinct structural characteristics (extended select gate electrode) localized to specific areas. In this local zone, contact holes can be formed with optimized depth and diameter for low resistance, while the rest of the device maintains the thin interlayer insulating film structure for high density. Each region has tailored properties suited to its function.
Data Source
AI summary
Technique of improving a manufacturing yield of a semiconductor device including a non-volatile memory cell in a split-gate structure is provided. A select gate electrode of a CG shunt portion is formed so that a second height d2 from the main surface of the semiconductor substrate of the select gate electrode of the CG shunt portion positioned in the feeding region is lower than a first height d1 of the select gate electrode from the main surface of the semiconductor substrate in a memory cell forming region.