Split-Gate SiC VDMOSFET Layout for Lower RON and Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In high-power silicon carbide vertical double-diffused metal-oxide semiconductor-field-effect transistor (VDMOSFET) devices, channel resistance remains a significant contributor to overall resistance, and existing methods to reduce on-resistance (RON) are limited by alignment errors and parasitic capacitance in the manufacturing process.
Innovation Solution
A semiconductor device manufacturing method involving the formation of an epitaxial layer with a split gate structure, where multiple doping regions and gates are formed through self-alignment processes, reducing parasitic capacitance and ensuring precise dimensions of the channel and doping regions, and the gate structure is designed to cover the channel region without overlapping the junction field effect transistor region, thereby minimizing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional manufacturing methods are used to form gates and doping regions, then the manufacturing process is simpler, but alignment errors increase and parasitic capacitance increases
Solution Approach 1:
The gate structure is divided into two separate gates (first gate and second gate) positioned on opposite sides of the drift region. This segmentation allows each gate to be independently formed with precise alignment to the channel region, reducing cumulative alignment errors that would occur in conventional single-gate structures. The segmentation also enables better control over parasitic capacitance by optimizing the position and dimensions of each gate separately.
Solution Approach 2:
The patent introduces a vertical dimension to the gate structure by forming gates on both sides of the drift region, effectively transitioning from a planar single-gate configuration to a three-dimensional split-gate configuration. This dimensional change allows for reduced parasitic capacitance while maintaining precise alignment through self-aligned formation processes, resolving the contradiction between manufacturing precision and device complexity.
2Reliability
If the gate structure is extended to cover more of the channel region, then control over the channel is improved, but parasitic capacitance increases
Solution Approach 1:
The gate control is segmented into two separate gates positioned on opposite sides of the drift region, each covering a portion of the channel region. This segmentation provides effective channel control through the combined action of both gates while minimizing parasitic capacitance by reducing the total gate-to-drift region overlap area compared to a single extended gate structure.
Solution Approach 2:
Each gate is locally optimized to cover specific portions of the channel region with precise dimensions and positioning. The local quality of gate coverage is maximized where needed for channel control while minimizing parasitic capacitance in other areas, achieving both improved reliability and reduced harmful effects through localized optimization.
3Loss of energy
If the channel length is shortened to reduce on-resistance, then the on-resistance decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions to a vertical channel structure with gates positioned on opposite sides, effectively utilizing the vertical dimension to achieve short channel lengths while maintaining precise control. This dimensional change allows for reduced on-resistance through shorter channel lengths without proportionally increasing manufacturing precision requirements, as the self-aligned formation process maintains accuracy in the reduced dimensions.
Solution Approach 2:
The manufacturing process employs self-aligned formation methods where the split gate structure and doping regions are automatically positioned relative to each other without requiring additional alignment steps. This self-service approach maintains high manufacturing precision even as channel length is reduced, allowing on-resistance to decrease without proportionally increasing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces parasitic capacitance and channel resistance, enhancing the switching rate and reducing power loss in high-voltage applications by ensuring precise alignment and dimensions of the doping and channel regions, thus improving the reliability and performance of the semiconductor device.
Implementation Method 1
performing an oxidation process to form an oxide layer on a surface of the hard mask layer
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming an epitaxial layer on a substrate, forming a hard mask on the epitaxial layer, in which the hard mask includes a first portion and a second portion, with a gap therebetween, performing an oxidation process to form an oxide layer on a surface of the hard mask, forming a source region in the epitaxial layer through the gap of the hard mask, forming a well region in the epitaxial layer using the second portion of the hard mask as a mask, forming a sacrificial layer on the source region and the well region, removing the second portion of the hard mask, forming a JFET region in the epitaxial layer using the sacrificial layer as a mask, forming a dielectric layer on the JFET region, removing the sacrificial layer and forming a gate structure adjacent the dielectric layer.