Split-Gate Memory Select Gate Sidewall Metal Silicide Resistance Reduction
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Solution Overview
Problem
Split-gate non-volatile memory (NVM) cells face challenges in reducing select-gate wordline resistance and improving electrical contact, which limits their performance and scalability, especially in thin film storage systems.
Innovation Solution
The formation of metal silicide regions within the sidewall and top portions of select gates, along with potential notches, reduces the select-gate wordline resistance by expanding the metal silicide surface area through spacer etch processing and annealing, enabling self-aligned salicide formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional split-gate NVM cell structures are used, then the device can be manufactured with standard processes, but the select-gate wordline resistance is high and electrical contact is poor
Solution Approach 1:
The select gate is divided into multiple segments with metal silicide regions formed at specific locations (sidewall portions and top portions) rather than as a continuous structure. This segmentation allows strategic placement of low-resistance metal silicide contacts at critical points along the select gate wordline, reducing overall resistance while maintaining structural integrity and enabling standard manufacturing processes.
Solution Approach 2:
Metal silicide regions are selectively formed only at specific locations of the select gate (sidewall and top portions) rather than uniformly across the entire gate structure. This local application of metal silicide provides enhanced electrical contact and reduced resistance precisely where needed in the wordline path, while avoiding unnecessary complexity in other regions.
2Reliability
If the select-gate wordline resistance is reduced by adding metal silicide regions, then electrical contact improves, but the manufacturing process becomes more complex
Solution Approach 1:
The metal silicide regions are formed during the gate fabrication process itself, before subsequent processing steps. The spacer etch processing exposes sidewall portions of the select gate in advance, and metal silicide is deposited and annealed to form low-resistance regions. This preliminary formation of metal silicide contacts integrates the resistance-reduction feature into the standard manufacturing flow without requiring separate post-processing steps.
Solution Approach 2:
The spacer structure serves a dual purpose: it provides structural definition for the gate and simultaneously creates the exposed sidewall portions that receive metal silicide regions. The spacer etch process automatically exposes the necessary sidewall areas without requiring additional patterning steps, allowing the structure to self-generate the conditions needed for metal silicide formation.
3Productivity
If standard split-gate NVM structures are used, then manufacturing is simpler, but scaling to smaller dimensions becomes difficult
Solution Approach 1:
Metal silicide regions are strategically placed at sidewall and top portions of the select gate where they provide the most benefit for scaling. This local enhancement of electrical contact at critical interfaces allows the device to scale to smaller dimensions while maintaining adequate wordline resistance characteristics, as the metal silicide compensates for reduced dimensional tolerances.
Solution Approach 2:
The invention extends the metal silicide formation from the traditional planar top surface into the vertical dimension by forming metal silicide regions in the sidewall portions of the select gate. This three-dimensional placement of metal silicide provides additional contact area and resistance reduction pathways that enable scaling to smaller dimensions without proportionally increasing resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the electrical contact and reduces the resistance of the select-gate wordline, improving the performance and controllability of split-gate NVM arrays, overcoming scaling limitations and enabling high-speed switching.
Implementation Method 1
forming a metal silicide region within the exposed sidewall portion of the select gate by reacting a thin metal film with the exposed sidewall portion through a series of annealing processes
Implementation Method 2
reacting a thin metal film with the exposed sidewall portion through a series of annealing processes to form a metal silicide region
Data Source
AI summary
Split-gate non-volatile memory (NVM) cells having select-gate sidewall metal silicide regions are disclosed along with related manufacturing methods. Spacer etch processing steps are used to expose sidewall portions of select gates. Metal silicide regions are then formed within these sidewall portions of the select gates. Further, metal silicide regions can also be formed in top portions of the select gates. Further, the select gates can also be formed with one or more notches. By expanding the size of the metal silicide region to include the sidewall portion of the select gate, the select gate wordline (e.g., polysilicon) resistance is reduced for split-gate NVM arrays, the electrical contact to the select gate is improved, and performance of the select-gate NVN cell is improved.