Split-Gate Semiconductor Structure With Oxide-Free Source Contacts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional manufacturing methods of semiconductor devices with split gates result in residual oxide regions that block conductive plugs from connecting to the low-voltage source, leading to abnormal device operation.
Innovation Solution
The method involves forming a first silicon nitride layer, etching it back to create a residual silicon nitride layer, followed by a silicon oxide layer and a second silicon nitride layer, and then etching these layers to form split gates, with a contact etch stop layer of silicon nitride to ensure complete removal of residual layers and enable electrical connection of conductive plugs to the low-voltage source.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a silicon oxide layer is formed and etched to form split gates with sufficient thickness (at least 600 Å), then the breakdown voltage characteristics of the high-voltage device are improved, but residual oxide regions remain in narrow spaces between low-voltage gates, blocking conductive plugs from contacting the low-voltage source
Solution Approach 1:
The patent segments the etching process into multiple sequential steps with different etching conditions. First, a preliminary etching step removes the silicon oxide layer partially, then a second etching step with modified parameters (such as different chemistry or power settings) completely removes residual oxide in narrow spaces between low-voltage gates. This segmented approach allows the split gate oxide to maintain sufficient thickness for high-voltage device reliability while ensuring complete removal in critical contact regions.
Solution Approach 2:
The patent applies preliminary action by performing a first etching step that partially removes the silicon oxide layer before the final etching step. This preliminary etching creates initial openings and reduces the overall oxide thickness, making subsequent complete removal in narrow spaces feasible. The preliminary action prepares the structure for the final precise etching that ensures conductive plug contact without compromising the split gate functionality.
2Manufacturing precision
If the silicon oxide layer thickness is reduced to enable complete removal in narrow spaces, then conductive plugs can contact the low-voltage source, but the breakdown voltage characteristics of the high-voltage device deteriorate
Solution Approach 1:
The patent segments the etching process into multiple steps with progressively different parameters. The first etching step uses conditions that remove oxide at a controlled rate, while the second etching step uses more aggressive conditions (such as different chemistry, higher power, or longer duration) specifically targeted at removing residual oxide in narrow spaces. This segmentation allows achieving complete removal without uniformly reducing the split gate oxide thickness that is critical for breakdown voltage characteristics.
Solution Approach 2:
The patent applies local quality by making the etching process location-dependent. The multi-step etching approach creates different local outcomes: in regions with split gates, sufficient oxide thickness is maintained for high-voltage operation, while in narrow spaces between low-voltage gates, complete oxide removal is achieved. The etching parameters are optimized to produce different removal depths in different locations, ensuring both contact hole formation and split gate functionality.
3Ease of manufacture
If a single etching process is used to form split gates, then the manufacturing process is simplified, but residual oxide regions block conductive plugs from contacting the low-voltage source
Solution Approach 1:
The patent segments the single etching process into multiple sequential etching steps, each with optimized parameters for specific objectives. The first etching step forms the initial split gate structure, while the second etching step ensures complete oxide removal in narrow spaces. Although this increases process steps, each step uses standardized etching equipment and chemistry, maintaining relative ease of manufacture while solving the residual oxide blocking problem.
Solution Approach 2:
The patent maintains continuity of useful action by performing etching steps in sequence without interrupting the overall manufacturing flow. The multi-step etching process is integrated into the existing fabrication sequence, with each step building upon the previous one. This continuous approach ensures that the split gate structure is formed and refined in a streamlined manner, achieving complete oxide removal while maintaining manufacturing efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents the blockage of conductive plugs by residual oxide regions, ensuring proper electrical connection and operation of the low-voltage device, while also integrating a metal-insulator-polysilicon capacitor and optimizing gate and oxide region thicknesses for improved performance.
Implementation Method 1
the silicon oxide layer 17 and the metal layer 18 are etched by an etching process to form two split gates SG1
Implementation Method 2
a common low-voltage source 14a and two low-voltage drains 15a of the low-voltage device LV1 are formed in the substrate 11
Data Source
AI summary
A manufacturing method of an integrated structure of semiconductor devices having split gates includes: forming a first silicon nitride layer covering a low voltage device and a high voltage device; etching back the first silicon nitride layer by an etching process step to form a residue silicon nitride region between two adjacent low voltage gates; forming a silicon oxide layer, a second silicon nitride layer, and a metal layer; forming two split gates by an etching process step; forming a contact etch stop layer (CESL); etching the CESL by an etching process step to form plural contacts in the CESL, wherein the contact between the two adjacent low voltage gates exposes at least part of a top surface of a common low voltage source on a substrate; and forming plural conductive plugs in the plural contacts respectively, wherein each of the conductive plug fills up the corresponding contact.


