Split-Gate Flash Memory Structure With Nested Source Line Coupling
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Solution Overview
Problem
The performance of existing split gate flash memory is poor, requiring improvements in programming efficiency and memory size reduction to align with semiconductor device miniaturization trends.
Innovation Solution
The memory design includes a floating gate structure with a first gate structure extension, a source line structure coupled perpendicular to the substrate, and an erasing gate structure with an isolation structure, reducing the floating gate's surface area and eliminating the need for high voltage in the word line gate structure, thereby enhancing programming efficiency and minimizing memory size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the floating gate structure uses a conventional layout, then the memory can be formed, but the programming efficiency is poor and the memory size is large
Solution Approach 1:
The source line structure extends in the first direction beyond the floating gate structure, and the first gate structure extends in the second direction perpendicular to the first direction. This three-dimensional arrangement increases coupling efficiency between the source line and floating gate without increasing the planar footprint, thereby improving programming efficiency while maintaining compact memory size.
Solution Approach 2:
The first gate structure is disposed on the second region and extends in the second direction, with the source line structure disposed on the first gate structure. This nested arrangement allows multiple functional structures to occupy overlapping spatial regions, maximizing space utilization and reducing overall memory area while enhancing electrical coupling.
2Reliability
If the word line gate structure requires high voltage for operation, then the memory function is maintained, but the channel current and width increase leading to larger memory area
Solution Approach 1:
The isolation structure is disposed on the third region and selectively isolates the word line gate structure, creating localized electrical boundaries. This allows the word line gate to operate with reduced channel width and lower current requirements in specific regions, reducing the overall memory area while maintaining necessary memory functionality through localized field control.
Data Source
AI summary
The present disclosure provides a memory and a method for forming the same. The memory includes: a substrate including a first region, a second region and a third region; a floating gate structure disposed on the second region of the substrate; a first side wall disposed on the floating gate structure; a first gate structure disposed on a side of the floating gate structure, wherein the first gate structure is electrically coupled with the floating gate structure; a dielectric structure disposed on a surface of the first gate structure; a source line structure disposed on a surface of the dielectric structure, wherein the source line structure is also disposed on a surface of the first region; and a word line gate structure disposed on the third region. Therefore, the performance of the memory can be improved.