Split-Gate Flash Cell Fabrication With Self-Aligned Spacer Gates
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Solution Overview
Problem
Traditional methods for fabricating split gate flash memory cells are costly due to numerous processing steps, including patterned masking and dry etching, which also cause damage to the silicon substrate and do not form self-aligned gate structures efficiently.
Innovation Solution
A method that forms split gate memory cells with fewer process steps by using a sacrificial spacer compatible with the silicon substrate, resulting in self-aligned gate structures with non-planar top surfaces and symmetric word gate pairs, eliminating the need for masked lithography steps and reducing substrate damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional patterned masking and dry etching steps are used to form split gate structures, then manufacturing precision can be achieved, but the number of processing steps increases and fabrication cost increases
Solution Approach 1:
A sacrificial spacer is formed beforehand at the desired location where the split gate structure needs to be created. This preliminary structure serves as a template that guides subsequent material deposition, eliminating the need for complex patterned masking and dry etching steps while maintaining manufacturing precision.
Solution Approach 2:
The sacrificial spacer automatically defines the geometry and position of the split gate structure through self-aligned deposition processes. The spacer itself serves as the patterning element, eliminating the need for separate photolithography and etching steps, thereby reducing device complexity while preserving precision.
2Manufacturing precision
If traditional dry etching and patterned masking are employed, then gate structures can be formed, but damage to the silicon substrate occurs
Solution Approach 1:
The mechanical dry etching process is replaced with a chemical deposition approach. Materials are deposited conformally over the sacrificial spacer, and the spacer is subsequently removed chemically, avoiding the mechanical stress and plasma damage associated with traditional dry etching while maintaining gate structure formation precision.
Solution Approach 2:
The sacrificial spacer acts as an intermediary structure that enables gate formation without direct contact between etching tools and the silicon substrate. By depositing materials over the spacer and removing the spacer afterward, the substrate is protected from harmful etching effects while the desired gate structure is achieved.
3Productivity
If fewer processing steps are used to reduce fabrication cost, then manufacturing efficiency improves, but manufacturing precision may deteriorate
Solution Approach 1:
Multiple traditional processing steps (photolithography, pattern transfer, etching) are merged into a single self-aligned deposition and spacer removal process. This consolidation reduces the total number of steps improving productivity, while the sacrificial spacer ensures precise gate structure formation is maintained through self-alignment.
Data Source
AI summary
The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a source/drain region arranged within a substrate. A select gate and a memory gate are arranged over the substrate. An inter-gate dielectric structure is arranged between the memory gate and the select gate. A conductive contact is disposed on the source/drain region and vertically extends from a bottom of the select gate to a top of the select gate. The select gate is closer to the conductive contact than the memory gate. The select gate has a first outermost sidewall that faces away from the memory gate and a second outermost sidewall that faces the memory gate. The first outermost sidewall is taller than the second outermost sidewall.