Split Gate Contacts for Independent Control in Stacked CMOS
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Solution Overview
Problem
Forming electrical contacts to both transistors in vertically stacked CMOS devices is challenging due to the stacked arrangement, which limits independent control and functionality.
Innovation Solution
The use of dielectric barriers to electrically isolate the gates of vertically stacked transistors, allowing separate access and formation with different materials, enabling independent control and tuning of electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single gate contact is used to access both top and bottom gates in vertically stacked transistors, then wiring complexity is reduced, but independent control of the transistors is lost
Solution Approach 1:
The gate barrier structure is segmented into a first portion extending between source/drain regions and a second portion extending over the channel, allowing separate electrical access to top and bottom gates through distinct contact regions while maintaining physical separation for independent control
Solution Approach 2:
The gate barrier acts as an intermediary structure that provides both electrical isolation between gates and pathways for separate contacts, enabling independent gate control without requiring complex external wiring arrangements
2Quantity of substance
If vertically stacked transistor configuration is used, then device density is increased, but forming interconnects without unintended short-circuits becomes challenging
Solution Approach 1:
The gate barrier is divided into distinct portions (first portion between source/drain, second portion over channel) that can be selectively contacted, enabling separate interconnect formation to top and bottom gates without short-circuits while maintaining high device density
Solution Approach 2:
Different regions of the gate barrier are designed with different properties - the first portion provides electrical isolation between source/drain regions, while the second portion provides a platform for gate contacts, allowing localized optimization for both density and manufacturability
3Adaptability or versatility
If gates are electrically isolated using dielectric barriers, then independent control is enabled, but fabrication complexity increases
Solution Approach 1:
The gate barrier is formed as a segmented structure with distinct portions serving different functions, allowing independent control of gates while the segmented design enables modular fabrication processes that reduce overall complexity
Solution Approach 2:
The gate barrier structure performs multiple functions simultaneously - providing electrical isolation, enabling separate contacts, and defining gate regions - which simplifies fabrication by consolidating multiple required functions into a single integrated structure
Data Source
AI summary
Semiconductor devices and methods of forming the same include a top transistor that includes a first channel and a first gate. A bottom transistor includes a second channel and a second gate that has a top surface at a same height as a top surface of the first gate. A gate barrier includes a horizontal part between the bottom transistor and the top transistor and a vertical part that extends from the horizontal part to a same height as the top surfaces of the first gate and the second gate.