Split Gate Transistor Layout for DRAM Integration
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Solution Overview
Problem
Current dynamic random access memory (DRAM) designs face challenges in reducing leak current and achieving high integration and density, as they typically have a single gate controlling the switch on/off function, limiting the accommodation of additional circuits to control transistors beyond bit lines and word lines.
Innovation Solution
A novel transistor circuit layout structure is proposed, featuring a substrate with a transistor having a split gate with independent blocks, bit lines, word lines, and back lines, where the horizontal levels of the back lines differ from those of the bit and word lines, allowing for additional circuits to control transistors and reduce leak current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single gate structure is used in conventional DRAM transistors, then the device complexity is low and manufacturing is easier, but the ability to accommodate additional control circuits is limited and leak current cannot be sufficiently reduced
Solution Approach 1:
The gate structure is divided into multiple independent gates (first gate, second gate, third gate) that can be controlled by separate control lines. This segmentation allows each gate to independently control different aspects of transistor operation, enabling additional control circuits to be accommodated while maintaining manageable device complexity through modular design
Solution Approach 2:
The patent introduces a vertical stacking dimension by placing multiple gates at different heights and positions around the channel region. The first gate is positioned at a first height, the second gate at a second height, and the third gate at a third height, creating a three-dimensional gate structure that accommodates multiple control circuits without significantly increasing planar footprint
2Reliability
If conventional single-gate transistor structures are used, then the layout is simpler, but leak current reduction capability is insufficient for high-performance DRAM
Solution Approach 1:
The transistor gate is segmented into multiple independent gates (first gate, second gate, third gate) that can be controlled by separate control lines. This segmentation allows each gate to independently control different aspects of transistor operation, enabling better leak current suppression through coordinated gating while maintaining manageable complexity through modular design
Solution Approach 2:
The multiple gates act as intermediaries between the control circuits and the channel region. Each gate can be independently controlled to modulate the electric field in the channel, providing fine-grained control over carrier flow and enabling effective leak current suppression through coordinated gating operations
3Reliability
If more control circuits are added to reduce leak current, then DRAM performance improves, but the integration density and area utilization deteriorate
Solution Approach 1:
The patent transitions from a planar gate arrangement to a vertical three-dimensional structure. Multiple gates are positioned at different heights around the channel region, allowing control circuits to be stacked vertically rather than spread horizontally. This significantly improves area utilization and integration density while accommodating the additional control circuits needed for enhanced DRAM performance
4Productivity
If conventional DRAM transistor layouts are used, then manufacturing processes are simpler, but integration and density requirements for miniaturized electronic products cannot be met
Solution Approach 1:
The invention employs vertical stacking of multiple gates and control circuits in the height dimension, enabling high integration and density without proportionally increasing planar footprint. This three-dimensional layout approach meets the demanding integration requirements for miniaturized electronic products while maintaining relatively simple manufacturing processes through standard semiconductor fabrication techniques
Solution Approach 2:
The patent implements a nested structure where multiple gates and control circuits are arranged concentrically around the channel region at different vertical levels. The first gate, second gate, and third gate are positioned at different heights, creating a compact nested configuration that maximizes integration density while keeping the overall device footprint small
Data Source
AI summary
A transistor circuit layout structure includes a transistor disposed on a substrate and including a source terminal, a drain terminal and a split gate including an independent first block and an independent second block, a bit line disposed on the source terminal and on the drain terminal or embedded in the substrate, a word line disposed on the first block, and a back line disposed on the second block. The horizontal level of the back line is different from that of the bit line and the word line.