Split-Gate Transistor STI Defect Mitigation via Etch-Back
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Solution Overview
Problem
High voltage semiconductor devices with shallow trench isolation (STI) regions are prone to defects such as needle, cone, or pillar defects during fabrication, leading to reduced oxide layer thickness between the defects and the gate electrode, resulting in electrical breakdown and decreased performance, reliability, and yield.
Innovation Solution
A split-gate transistor configuration with a mask-defined area within the STI region is used to partially etch back the defects, increasing the oxide layer thickness by reducing the defect height, and a polysilicon etch step is employed to minimize the height of needle defects, thereby reducing the transistor's sensitivity to STI defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the trench is filled with oxide and gate electrode is deposited over the region including the defect, then the manufacturing process is completed, but electrical breakdown between the defect and gate electrode occurs due to reduced separation
Solution Approach 1:
The patent applies preliminary action by performing an etch-back process to remove the oxide layer and reduce defect height before the gate electrode is deposited. This提前 removes the harmful defect structure that would otherwise cause electrical breakdown, allowing the subsequent gate deposition to proceed without reliability issues.
Solution Approach 2:
The patent converts the harmful effect of the defect (which reduces oxide thickness and causes breakdown) into a beneficial outcome by selectively removing the defect through etch-back processing. The defect material is transformed from a harmful element into removable waste, eliminating the reliability problem while maintaining manufacturing efficiency.
2Manufacturing precision
If tight physical tolerances are maintained between the defect, gate electrode and active areas, then device performance is optimized, but the defect sensitivity remains problematic
Solution Approach 1:
The patent applies the extraction principle by removing the defect from the structure through selective etch-back processing. The defect material is extracted and removed from the trench region, eliminating the source of sensitivity problems while maintaining the tight physical tolerances needed for device performance.
Solution Approach 2:
The patent applies local quality by selectively treating only the defect region through mask-defined etch-back processing. The mask ensures that only the area containing the defect is etched, while surrounding areas maintain their original structure and tight tolerances, achieving local defect removal without affecting overall device precision.
3Reliability
If the oxide layer thickness is increased to prevent breakdown, then reliability improves, but the separation between gate electrode and defect must be increased
Solution Approach 1:
The patent applies preliminary action by reducing the defect height through etch-back before gate deposition. This提前 reduction of defect height allows the oxide layer to maintain adequate thickness for reliability without requiring increased separation distance, as the defect no longer protrudes into the gate oxide region.
Solution Approach 2:
The patent applies parameter changes by modifying the defect geometry (height) through etch-back processing. By changing the defect height parameter from protruding to recessed, the system achieves adequate oxide thickness for reliability without increasing the horizontal separation distance, maintaining compact device dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces the transistor's sensitivity to STI defects by increasing the oxide layer thickness, minimizing leakage paths, and preventing dielectric breakdown, thereby enhancing the performance, reliability, and yield of high voltage semiconductor devices.
Implementation Method 1
thermally oxidizing the trench to form a silicon oxide layer
Implementation Method 2
removing the top portion of the defect with a semiconductor etch, thereby increasing a vertical separation between the gate electrode and the defect
Data Source
AI summary
A method for reducing transistor sensitivity to shallow trench isolation defects (STI) includes filling a trench formed in a substrate of a semiconductor device, at least partially, with a first oxide, the trench defines an STI and includes a defect extending from the substrate. A mask defines a planar area within the isolation region including a first lateral distance between an edge of the mask and an edge of the isolation region. The first oxide is at least partially removed beneath the planar area with an oxide etch to expose a top portion of the defect. The top portion of the defect is removed with a semiconductor etch. After removing the top portion of the defect, the trench is at least partially filled with a second oxide. A field plate of a split-gate transistor is formed over the STI.