Split-Gate VDMOS Trench Structure for Reduced Lithography Complexity
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Solution Overview
Problem
The existing split-gate VDMOS technology increases processing costs and implementation difficulties due to the need for additional polysilicon lithography layers and the formation of steps on the wafer surface during the leading-out of electrodes.
Innovation Solution
A method for manufacturing a VDMOS device that forms a trench with distinct regions for deep and shallow gates, using insulating and polysilicon layers to isolate and expose the electrodes without increasing polysilicon lithography layers, allowing for separate leading-out of the electrodes while maintaining all polysilicon gates within the trench.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If additional polysilicon lithography layers are used to separate the two gates, then the gates can be led out to different electrodes, but the processing cost increases
Solution Approach 1:
The gate structure is segmented into a first gate (deep trench gate) and a second gate (shallow trench gate) that are formed separately and led out to different electrodes. This segmentation allows each gate to be independently controlled and connected to different electrodes, achieving the desired gate separation functionality without requiring additional polysilicon lithography layers beyond the standard process
Solution Approach 2:
The patent utilizes the vertical dimension by forming gates at different depths within the trench structure. The first gate extends deeper into the substrate while the second gate remains shallower, allowing both gates to be formed within the same polysilicon lithography layer but at different vertical positions, thereby achieving gate separation without increasing the number of lithography layers
2Ease of operation
If the shallow trench-like gate is led out to the periphery and punched out, then the gate can be connected to the electrode, but a step is formed on the wafer surface affecting subsequent processes
Solution Approach 1:
The patent embeds both the first gate and second gate within the trench structure, with the gates nested at different depths. The shallow gate is positioned within the trench region and connected to its electrode through the trench structure itself, rather than being led out to the wafer surface. This nesting approach eliminates the need for surface-level gate leading-out and punching operations, thereby maintaining wafer surface flatness and avoiding steps that would interfere with subsequent processing
3Manufacturing precision
If all polysilicon gates remain within the trench, then surface steps are eliminated, but the electrode separation becomes more difficult
Solution Approach 1:
The patent applies different structural characteristics to different regions within the trench. The first gate region is designed with deeper extension and different connectivity than the second gate region. By giving each gate region its own local structural quality, the patent enables both gates to remain within the trench while still achieving effective separation and independent connection to different electrodes
Data Source
AI summary
A VDMOS device and a manufacturing method therefor. The method comprises: forming a groove in a semiconductor substrate, wherein the groove comprises a first groove area, a second groove area and a third groove area communicating with the first groove area and the second groove area, and the width of the first groove area is greater than the widths of the second groove area and the third groove area; forming an insulation layer on the semiconductor substrate; forming a first polycrystalline silicon layer on the insulation layer; removing some of the first polycrystalline silicon layer; the first polycrystalline silicon layer forming in the first groove being used as a first electrode of a deep gate; removing all the insulation layer located on the surface of the semiconductor substrate and some of the insulation layer located in the groove; forming a gate oxide layer on the semiconductor substrate; forming a second polycrystalline silicon layer on the gate oxide layer; removing some of the second polycrystalline silicon layer; and the second polycrystalline silicon layer forming in the groove being used as a second electrode of a shallow gate.