Split Gate Memory Voltage Breakdown Prevention
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Solution Overview
Problem
Split gate memory cells face voltage breakdown issues due to the weak spot in the gap region between the select gate and control gate, which is subjected to repeated high erase voltage during non-volatile memory cell operation.
Innovation Solution
Increasing the gap between the upper corner of the control gate and the split gate and filling this increased gap with a high-quality dielectric material to prevent voltage breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the gap between select gate and control gate is reduced to improve device integration, then device complexity and integration are improved, but voltage breakdown risk increases due to the weak spot in the gap region subjected to repeated high erase voltage
Solution Approach 1:
The patent applies local quality by making the dielectric material in the gap region between the select gate and control gate different from other regions. Specifically, a first dielectric material is formed in the gap region and a second dielectric material is formed in the trench region, where the first dielectric material has different properties (typically higher quality or different composition) to specifically address the voltage breakdown issue in this critical weak spot region.
Solution Approach 2:
The patent uses composite materials by combining two different dielectric materials in the same memory device structure. The first dielectric material is placed in the gap region between gates, while the second dielectric material fills the trench region. This composite approach allows optimization of each region's electrical properties, with the first material providing enhanced voltage breakdown resistance where needed most.
2Adaptability or versatility
If high erase voltage is applied to achieve non-volatile memory operation, then memory programming and erasing functions are achieved, but voltage breakdown occurs in the gap region which is repeatedly subjected to high voltage stress
Solution Approach 1:
The patent applies local quality by making the dielectric material in the gap region between the select gate and control gate different from other regions. Specifically, a first dielectric material is formed in the gap region and a second dielectric material is formed in the trench region, where the first dielectric material has different properties (typically higher quality or different composition) to specifically address the voltage breakdown issue in this critical weak spot region.
Solution Approach 2:
The patent applies beforehand cushioning by pre-forming a high-quality dielectric material in the gap region before the memory device undergoes repeated high voltage erase operations. This first dielectric material acts as a protective cushion that prevents voltage breakdown from occurring during subsequent high stress operations, allowing the device to withstand the necessary high erase voltages for non-volatile memory functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents voltage breakdown in split gate memory cells by enhancing the gap distance and using a higher quality dielectric, thereby improving the reliability and durability of the memory cells.
Implementation Method 1
filling this increased gap with a high-quality dielectric material to prevent voltage breakdown
Data Source
AI summary
A split gate memory cell comprising a substrate including semiconductor material and a first gate structure of the memory cell located over the substrate. The first gate structure includes a first side wall having a lower portion and an upper portion. The upper portion is inset from the lower portion. A charge storage structure of the memory cell is located laterally to the first side wall. A second gate structure is located over the substrate and over at least a portion of the charge storage structure. The second gate structure is located laterally to the first gate structure such that the first side wall is located between the first gate structure and the second gate structure. A dielectric structure located against the upper portion of the first side wall and has a portion located over the lower portion of the first side wall.