Splitting Hardware Interrupts to Separate Send and Receive Handlers
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Solution Overview
Problem
Existing interrupt handler systems are limited by a single thread that processes both send and receive events sequentially, leading to increased latency and reduced throughput due to the need for a single queue for completing data processing from both types of events.
Innovation Solution
Implementing separate queues and threads for send and receive events, allowing for simultaneous and independent processing of send and receive data through dedicated send and receive handlers, which manage their respective completion queues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single thread processes both send and receive events sequentially, then the system structure is simple, but the processing latency increases and throughput decreases
Solution Approach 1:
The patent divides the single interrupt handler into multiple separate handlers (send handler and receive handler), each dedicated to processing specific event types. This segmentation allows parallel processing of send and receive events, reducing processing latency while maintaining manageable system complexity through clear functional separation.
Solution Approach 2:
The patent transitions from sequential processing (single dimension) to parallel processing by introducing multiple threads that can execute simultaneously. This dimensional change from time-sequential to space-parallel architecture enables concurrent handling of different event types, improving throughput without proportionally increasing complexity.
2Device complexity
If a single queue handles both send and receive events, then the queue structure is simple, but the processing throughput is reduced
Solution Approach 1:
The patent segments the single event queue into multiple separate queues (send event queue and receive event queue), allowing dedicated processing threads to handle each queue independently. This increases throughput by eliminating contention and enabling parallel data flow, while the modular queue structure keeps complexity manageable through clear separation of concerns.
Solution Approach 2:
Each separate queue and its associated handler are designed to be universally applicable to their specific event type, with the overall system providing multi-functionality by handling both send and receive events through specialized components. This universal design within specialized contexts improves throughput while maintaining structural clarity.
3Device complexity
If a single interrupt handler processes all events, then the handler design is simple, but the processing efficiency decreases
Solution Approach 1:
The patent segments the monolithic interrupt handler into multiple specialized handlers (send handler, receive handler, and other event handlers), each optimized for specific event types. This segmentation improves processing efficiency by allowing concurrent execution and specialized optimization, while the modular design keeps overall complexity manageable through clear functional boundaries.
Solution Approach 2:
Each interrupt handler is designed with local quality - specialized processing logic tailored to its specific event type. The send handler is optimized for send events, the receive handler for receive events, and so on. This localized optimization improves overall processing efficiency while the distributed architecture prevents any single handler from becoming overly complex.
Data Source
AI summary
A method and apparatus are provided for reducing latency associated with processing events of a hardware interrupt. Send and receive events share the same hardware interrupt. A receive handler and a separate send handler are provided to simultaneously process completion of a send event and a receive event. In addition, separate queues are provided to communicate receipt of an event to the respective interrupt handler.