Split Integer Encoding in PE Arrays for Lower-Power Neural Arithmetic
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Solution Overview
Problem
Current neural network implementations face challenges in optimizing power and efficiency, particularly in optimizing performance and optimizing performance and efficiency, and in optimizing performance and optimizing performance, and in optimizing performance and optimizing performance and optimizing performance and optimizing performance and optimizing performance.
Innovation Solution
The solution is to implement a processing element with a processing unit with a processing element and optimizing performance and optimizing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If standard integer encoding is used in neural network processing elements, then hardware implementation is simple, but power consumption and computational efficiency are suboptimal
Solution Approach 1:
The patent changes the parameter representation from standard N-bit signed integers to a split-format encoding where the integer is divided into a higher order portion (N-M bits) and a lower order portion (M+1 bits). This parameter transformation enables more efficient power management and computational operations while maintaining hardware feasibility through structured bit allocation.
2Productivity
If fixed-width integer encoding is used, then hardware implementation is straightforward, but computational throughput and efficiency are limited
Solution Approach 1:
The patent segments the N-bit integer into two distinct portions: a higher order portion with N-M bits and a lower order portion with M+1 bits. This segmentation allows the arithmetic circuit to process the number in parts, enabling more efficient multiplication and accumulation operations that improve computational throughput while keeping the encoding structure manageable.
Solution Approach 2:
The encoding structure is designed to be dynamically adaptable, allowing the system to adjust the split between higher and lower order portions based on computational needs. The controller can manage the encoding flexibility to optimize throughput for different neural network operations without requiring complete hardware redesign.
3Ease of operation
If activation values are stored in separate memory blocks, then data access is simplified, but memory bandwidth requirements and data transfer overhead increase
Solution Approach 1:
The encoder is positioned between the activation memory and the PE array, performing preliminary encoding of activation values into the split-format before they reach the processing elements. This preliminary action allows the PE array to receive preprocessed data, reducing the immediate bandwidth requirements during computation while maintaining simplified memory access patterns.
Data Source
AI summary
A processing unit includes a processing element (PE) array having a plurality of rows of PEs and a plurality of columns of PEs. Each of the PEs includes an arithmetic circuit configured to mathematically combine activation operands and weight operands. The PE array also includes a weight memory configured to supply weight operands to PEs in the PE array, an activation memory configured to supply activation operands to PEs in the PE array, and an encoder coupled to the activation memory. The encoder includes a multiplexing circuit configured to encode a signed N-bit input activation as a signed N-M bit higher order portion representing the integer value [signed {aN-1 . . . aN-M}+aN-1]*2M and a signed M+1 bit lower order portion representing the integer value signed {aNaN-M-1 . . . a0}.