Split I/O Power Gating for Deep Sleep Configuration Retention
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Solution Overview
Problem
Processors continue to consume power even in low power modes due to I/O interfaces, as powering down these interfaces can result in loss of configuration or critical functions, especially when connected to devices like DDR memory that require continuous operation.
Innovation Solution
Separation of I/O logic into gated and ungated portions, where ungated logic remains powered to prevent configuration loss and critical functions are maintained, while gated logic is powered down during idle periods, utilizing a power control unit to manage this process in hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If I/O interfaces remain powered during processor deep sleep state, then configuration is maintained and critical functions continue to operate, but power consumption increases
Solution Approach 1:
The I/O module is divided into multiple independent power domains, with each domain controlled by separate power gating logic. This allows selective powering down of non-critical I/O interfaces while maintaining power to critical functions and configuration storage, resolving the contradiction between power savings and configuration retention.
Solution Approach 2:
Different power management strategies are applied to different regions of the I/O module based on their functional requirements. Critical interfaces maintain full power, non-critical interfaces are gated, and configuration storage receives conditional power, optimizing the balance between power consumption and reliability locally across the module.
2Use of energy by moving object
If I/O interfaces are powered down during idle periods, then power consumption decreases, but configuration loss and functional interruption occur
Solution Approach 1:
The system performs preliminary assessment of I/O interface criticality before entering deep sleep state. Power gating decisions are made in advance based on predetermined criteria, ensuring that configuration retention requirements are met before power is reduced, thus preventing configuration loss while achieving power savings.
Solution Approach 2:
Configuration storage elements act as intermediaries between powered-down I/O interfaces and the rest of the system. These elements maintain configuration data during power gating, allowing interfaces to be powered down without causing configuration loss, thus resolving the contradiction between power savings and reliability.
3Speed
If all I/O logic is kept powered during deep sleep, then system responsiveness is maintained, but average power usage increases
Solution Approach 1:
The power state of I/O interfaces is made dynamic rather than static. Interfaces transition between powered and powered-down states based on real-time system conditions and criticality assessments, allowing the system to optimize responsiveness versus power consumption dynamically during deep sleep and idle periods.
Solution Approach 2:
The system employs periodic monitoring and assessment of I/O interface requirements during deep sleep state. Power gating decisions are revisited at predetermined intervals, allowing the system to maintain responsiveness when needed while achieving power savings during extended idle periods, thus balancing speed and power usage.
Data Source
AI summary
I/O logic can be separated into critical and non-critical portions, with the non-critical portions being powered down during processor idle. The I/O logic is separated into gate logic and ungated logic, where the ungated logic continues to be powered during a processor deep sleep state, and the gated logic is powered off during the deep sleep state. A power control unit can trigger the shutting down of the I/O logic.