Split-Layer Stacked Transistors for Smaller GAA Nanosheet Footprints
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Solution Overview
Problem
There is a continued desire for further miniaturization and increased structural features in semiconductor devices, particularly in field-effect transistors, beyond the capabilities of existing technologies such as FinFETs and nanosheet stacks, to achieve improved performance and reduced size.
Innovation Solution
The development of stacked device structures with split device layers, including multi-stacked transistor structures and field-effect transistor structures, utilizing epitaxial growth and selective etching to form complex gate-all-around configurations, which allow for the formation of nanosheet channels and source/drain regions, enhancing structural gains and reducing device area footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional FinFET and nanosheet stack structures are used, then device functionality is maintained, but device area footprint is too large for further miniaturization
Solution Approach 1:
The transistor structure is segmented into multiple independent vertical stacks, each containing multiple channels. The gate is divided into separate gate regions that can be independently controlled. This segmentation allows for more efficient space utilization and enables further miniaturization while maintaining device functionality.
Solution Approach 2:
The invention transitions from planar 2D device layouts to three-dimensional vertical stacking architectures. Multiple channels are stacked vertically rather than arranged horizontally, effectively utilizing the third dimension to reduce the device footprint while increasing the number of functional channels per unit area.
2Productivity
If device density is increased through stacking, then miniaturization is achieved, but structural complexity increases
Solution Approach 1:
Multiple channel layers are nested vertically within a compact structure, with each channel surrounded by its own gate region. The channels are arranged in a nested configuration where lower channels are positioned beneath upper channels, maximizing space utilization while maintaining a relatively simple overall structural framework.
Solution Approach 2:
The stacked channel structure serves multiple functions simultaneously: it increases device density, provides multiple independent conduction paths, and enables independent gate control for each channel. This multi-functionality reduces the need for separate structural elements, thereby managing complexity while achieving high density.
3Productivity
If more channel layers are added to increase device density, then performance improves, but manufacturing precision requirements increase
Solution Approach 1:
The channel layers and gate regions are formed using a preliminary epitaxial growth process that establishes precise layer sequences and thicknesses before subsequent patterning steps. This preliminary structuring ensures accurate alignment and spacing between multiple channels, reducing the precision burden on later manufacturing steps.
Solution Approach 2:
The invention replaces traditional mechanical lithographic patterning with epitaxial growth methods to define channel positions and gate regions. This substitution enables atomic-level precision in layer formation and alignment, achieving the required manufacturing precision through self-organized crystal growth rather than mechanical positioning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables significant structural gains, such as 30-40% reduction in device area footprint, addressing the limitations of existing technologies and facilitating further scaling to 2.5 nm and beyond, while improving performance and reducing power consumption.
Implementation Method 1
utilizing epitaxial growth and selective etching to form complex gate-all-around configurations
Implementation Method 2
utilizing epitaxial growth and selective etching to form complex gate-all-around configurations
Data Source
AI summary
A semiconductor device includes a multi-stacked transistor structure comprising a first stacked transistor structure and a second stacked transistor structure. The first stacked transistor structure includes a first lower transistor device and a first upper transistor device, and the second stacked transistor structure includes a second lower transistor device, a second upper transistor device, and a third upper transistor device.