Split-Level Voltage Limiter for High-Speed Data ESD Protection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing ESD circuits in high-speed data communication applications, such as USB and Thunderbolt, face a challenge in meeting ESD standards while minimizing capacitance loading that limits signal bandwidth and return-loss.
Innovation Solution
A voltage limiting device with a split-level configuration of diodes, where diodes D3 and D4 form the upper portion and diode D5 forms the lower portion, coupled by a mid-net, reduces equivalent capacitance by selectively choosing the 'size' of diodes, thereby increasing bandwidth and return-loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ESD circuits are used to protect against electrostatic discharge, then ESD protection is provided, but capacitance loading increases which limits signal bandwidth and return-loss
Solution Approach 1:
The ESD protection circuit is segmented into multiple diode levels (first level with anode connected to data line, second level with anode connected to first level cathode, and third level with anode connected to second level cathode). This segmentation allows the circuit to provide comprehensive ESD protection while reducing the equivalent capacitance loading on the data line compared to a single-stage protection circuit.
2Reliability
If diode size is increased to provide sufficient ESD protection current capacity, then ESD protection level improves, but equivalent capacitance increases which reduces bandwidth
Solution Approach 1:
The protection circuit divides the ESD current handling into multiple stages with multiple diodes. Each diode can be optimized for lower individual capacitance while the series configuration provides cumulative ESD protection capability, achieving high ESD protection level with reduced equivalent capacitance.
Solution Approach 2:
Each diode in the multi-level structure can be independently sized and optimized. The diodes are configured with appropriate capacitance values for their specific position in the protection hierarchy, allowing local optimization of the trade-off between protection capability and capacitance loading.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The split-level configuration significantly reduces equivalent capacitance, enhancing bandwidth and return-loss by a factor of 3× compared to traditional topologies, while maintaining compliance with ESD standards.
Implementation Method 1
the current shunts are diodes
Implementation Method 2
The voltage limiting device is an electrostatic discharge (ESD) limiting device
Implementation Method 3
a negative voltage charge pump is coupled to the mid-net and configured to bias the mid-net with a negative voltage which reduces the capacitance of the voltage limiter
Data Source
AI summary
One example discloses a voltage limiting device, including: a first I/O port; a second I/O port; a voltage limiter, coupled to the first and second I/O ports, and configured to shunt a voltage received on the first and/or second I/O ports having an absolute value greater than a voltage limit; wherein the voltage limiter includes a first portion and a second portion; wherein the first portion includes a first current shunt coupled between the first I/O port and a mid-net, and a second current shunt coupled between the second I/O port and the mid-net; and wherein the second portion includes a third current shunt having one end coupled to the mid-net and another end coupled to a ground.