Split-Line Memory ECC Layout for Metadata Allocation
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Solution Overview
Problem
Increasing memory device density and operating speeds lead to higher runtime errors, with traditional ECC architectures consuming all available bits for error correction, leaving no capacity for system-level metadata, and alternative solutions like sequestered memory result in performance and capacity penalties.
Innovation Solution
Implementing split line access (SLAM) to distribute data across multiple parallel memory resources, reducing the number of ECC bits needed for error correction by splitting data into sub-portions, allowing metadata usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ECC architecture is used to provide single device data correction (SDDC), then error correction capability is improved, but all available bits are consumed for ECC, leaving no capacity for metadata
Solution Approach 1:
The patent divides data lines into multiple sub-portions and distributes them across multiple memory resources. By segmenting the data storage, the ECC requirements for each individual resource are reduced, freeing up bits that can be reallocated for metadata storage while maintaining overall error correction capability through the distributed architecture.
Solution Approach 2:
The patent introduces a new dimension to memory organization by implementing split line access that distributes data across multiple parallel memory resources rather than using a single resource. This dimensional change in data distribution allows for more efficient ECC utilization and creates capacity for metadata without compromising error correction.
2Productivity
If memory device density and operating speeds are increased, then data bandwidth per transaction is improved, but runtime errors increase
Solution Approach 1:
The patent segments data into multiple sub-portions stored across different memory resources, allowing parallel access that maintains high data bandwidth. The segmentation also distributes error risk, so that runtime errors affecting one resource do not compromise the entire data set, thereby maintaining reliability at higher speeds.
Solution Approach 2:
The patent combines multiple memory resources into a unified memory system that operates in parallel. This merging allows the system to achieve high data bandwidth through parallel access while maintaining reliability through distributed error correction across the combined resources.
3Quantity of substance
If sequestered memory is used to provide metadata capacity, then metadata storage is improved, but performance and capacity penalties are incurred
Solution Approach 1:
The patent makes memory resources universal by enabling them to serve multiple functions - storing both data sub-portions and metadata. Instead of dedicating separate sequestered memory regions that incur performance penalties, the same memory resources dynamically serve dual purposes through the split line access architecture, eliminating the performance-capacity tradeoff.
Data Source
AI summary
A memory subsystem includes multiple memory resources connected in parallel, including a first memory resource and a second memory resource. The memory subsystem can split a portion of data into multiple sub-portions. Split into smaller portions, the system needs fewer ECC (error checking and correction) bits to provide the same level of ECC protection. The portion of data can include N ECC bits for error correction, and the sub-portions can each include a sub-portion of (N−M) ECC bits for error correction. The system can then use M bits of data for non-ECC purposes, such as metadata.