Split-Load IR Optimization for Integrated Circuit Timing Margins
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Solution Overview
Problem
Existing integrated circuit design strategies struggle to effectively mitigate IR drop issues when timing margins are depleted, limiting the viability of conventional approaches like down-sizing cells and threshold voltage device swapping.
Innovation Solution
A split-load voltage (IR) optimization strategy that creates additional timing margin by splitting loads for extra IR drop reduction, addressing both IR and timing considerations to enhance overall design efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If down-sizing cells and threshold voltage device swapping are used to mitigate IR drop, then IR violations are reduced, but timing margins are depleted
Solution Approach 1:
The load is divided into two separate circuit components (first circuit component and second circuit component). The first circuit component handles critical timing paths while the second circuit component handles non-critical loads. This segmentation allows IR optimization without compromising timing margins on critical paths.
Solution Approach 2:
Different circuit components are assigned different functions based on their timing characteristics. The first circuit component is optimized for timing-critical paths while the second circuit component handles timing-noncritical paths. This local differentiation enables targeted IR drop reduction without affecting overall timing performance.
2Use of energy by moving object
If conventional IR optimization strategies are applied, then power consumption is reduced, but design efficiency deteriorates when timing margins are depleted
Solution Approach 1:
The invention changes the structural parameter of the circuit by splitting a single circuit component into two separate components with different timing characteristics. This parameter change enables continued IR optimization through load redistribution without depleting timing margins, thereby maintaining design efficiency.
3Device complexity
If load is concentrated in a single circuit component, then device complexity is reduced, but IR violations increase
Solution Approach 1:
The concentrated load is segmented into two separate circuit components. The first circuit component handles timing-critical loads while the second circuit component handles timing-noncritical loads. This segmentation reduces current density in each component, thereby reducing IR violations while maintaining manageable device complexity.
Data Source
AI summary
A method for designing an integrated circuit comprises identifying a first circuit component that presents a voltage (IR) drop being equal to or greater than an IR drop threshold through at least an IR drop analysis, splitting the plurality of timing paths into a first subset of timing paths and a second subset of timing paths, based on a timing margin threshold; and adding a second circuit component disposed along the second subset of timing paths, while keeping the first circuit component disposed along the first subset of timing paths. The first circuit component can be disposed along a plurality of timing paths that each extend from a first storage node and to a second storage node and can be each associated with a timing margin.