Split-Memory Error Detection for Address Fault Integrity
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Solution Overview
Problem
Existing methods for reading and writing data in memories are unreliable and inefficient in detecting errors, particularly accidental or intentional errors such as writing data to incorrect addresses, which can be exploited by attackers through fault injection processes.
Innovation Solution
A method where a binary word representing data and an error correction or detection code is split into two parts, with each part written to a different memory circuit, and internal control signals are compared to verify the integrity of the data and address, using redundant processors for error detection during read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is stored in a single memory circuit, then the device complexity is low, but the reliability of error detection is insufficient
Solution Approach 1:
The binary word is divided into two parts and stored in two separate memory circuits. This segmentation allows independent verification of each part through comparison of internal control signals, thereby improving error detection reliability while distributing the complexity across multiple simpler memory units rather than requiring a single complex memory system.
Solution Approach 2:
The invention creates redundant copies of data parts in separate memory circuits with identical structure. By comparing internal control signals from these duplicate memory circuits, the system can detect errors without requiring fundamentally different or more complex memory architecture, thus improving reliability without proportionally increasing device complexity.
2Reliability
If error detection codes are added to data, then the reliability of data integrity is improved, but the productivity of data processing is reduced
Solution Approach 1:
The memory circuits themselves perform error detection by comparing their internal control signals during normal read/write operations. This self-service mechanism eliminates the need for separate error detection processing steps, allowing data integrity verification to occur concurrently with data processing and thereby minimizing the impact on productivity.
Solution Approach 2:
The comparison of internal control signals from multiple memory circuits provides immediate feedback on data integrity during the storage operation. This feedback mechanism allows for real-time error detection without requiring additional processing cycles, thus maintaining data integrity while minimizing productivity loss.
3Reliability
If multiple memory circuits are used for storing data parts, then the capability to detect addressing errors is improved, but the ease of operation is reduced
Solution Approach 1:
The invention combines the error detection function with the existing data writing operation by comparing internal control signals during the write process itself. This merging allows addressing error detection to occur automatically as part of the normal write operation, eliminating the need for separate verification steps and thereby maintaining ease of operation while improving reliability.
Data Source
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AI summary
This description relates to a method of writing data (Datai) into memory, in which: - a binary word (Code1), representing said data (Datai) and an error-correcting or error-detecting code (EDC1), is split into at least a first and a second part (Code1A, Code1B); and - said first part (Code1A) is written to a logical address (AddL1) in a first memory circuit (105); and - said second part (Code1B) is written to said logical address in a second memory circuit (106) adapted to store as many binary words as said first memory circuit (105), said error-correcting or error-detecting code (EDC1) being dependent on said data (Datai) and said address (AddL1).