Split Memory Cells with Unsplit Select Gates in 3D NAND
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Solution Overview
Problem
Current three-dimensional non-volatile memory devices, such as vertical NAND strings, face challenges in achieving high density and efficient memory stack formation due to limitations in the existing methods for forming memory openings and selecting gate levels, which affect the performance and reliability of the memory devices.
Innovation Solution
The solution involves forming a three-dimensional memory device with a monolithic structure, including a substrate with alternating stacks of insulating and conductive layers, separator insulator structures, and memory stack structures, where the lower-select-gate-level spacer material layer is formed over the substrate, and etch stop layers are used to create memory openings that extend through the alternating stack, allowing for the formation of electrically conductive layers that function as select gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory openings are formed through alternating conductive and dielectric layers to create vertical NAND strings, then high-density three-dimensional storage is achieved, but gate-to-gate short circuits occur and threshold voltage variability increases
Solution Approach 1:
The patent divides the continuous conductive layer into segmented portions by introducing separator insulator structures between adjacent memory stack structures. This segmentation prevents electrical connection between adjacent select gates, eliminating gate-to-gate short circuits while maintaining high storage density through the three-dimensional stacked architecture
Solution Approach 2:
The patent introduces separator insulator structures as intermediary elements between adjacent memory stack structures. These insulator structures act as electrical barriers that prevent direct contact between conductive layers of adjacent stacks, thereby eliminating short circuits and reducing threshold voltage variability without compromising storage capacity
2Ease of operation
If select gates are formed by conductive layers in the alternating stack, then memory device functionality is achieved, but boost leakage occurs due to electrical connection between adjacent gates
Solution Approach 1:
The patent extracts or removes the electrical connection between adjacent select gates by introducing separator insulator structures. This extraction eliminates the harmful electrical pathway that causes boost leakage while preserving the necessary electrical connectivity within each individual memory stack structure for proper device functionality
Solution Approach 2:
The separator insulator structures serve as intermediary barriers between adjacent memory stack structures. These insulators block the unwanted electrical connection between select gates of adjacent stacks, preventing boost leakage while allowing each stack to maintain its own electrical functionality independently
3Reliability
If separator insulator structures are introduced to prevent gate short circuits, then threshold voltage variability is reduced, but device structure complexity increases
Solution Approach 1:
The patent merges the separator insulator structures with the existing alternating stack of conductive and dielectric layers. By integrating the separators into the layered structure rather than adding them as separate external components, the design achieves reduced threshold voltage variability while minimizing increases in overall device complexity
4Quantity of substance
If vertical NAND string architecture is used for high-density storage, then storage capacity is improved, but manufacturing precision requirements increase due to alignment challenges
Solution Approach 1:
The patent transitions from two-dimensional planar memory architecture to three-dimensional vertical stacked architecture. By stacking multiple memory layers vertically, the design achieves high storage capacity while the separator insulator structures provide reference planes that facilitate precise alignment during manufacturing processes
Data Source
AI summary
Split memory cells can be provided within an alternating stack of insulating layers and word lines. At least one lower-select-gate-level electrically conductive layers and/or at least one upper-select-level electrically conductive layers without a split memory cell configuration can be provided by limiting the levels of separator insulator structures within the levels of the word lines. At least one etch stop layer can be formed above at least one lower-select-gate-level spacer material layer. An alternating stack of insulating layers and spacer material layers is formed over the at least one etch stop layer. Separator insulator structures are formed through the alternating stack employing the etch stop layer as a stopping structure. Upper-select-level spacer material layers can be subsequently formed. The spacer material layers and the select level material layers are formed as, or replaced with, electrically conductive layers.