Power-to-Digital Converter Using Split MSB and LSB Conversion
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Solution Overview
Problem
Conventional power-to-digital converters (PDCs) occupy large silicon areas due to the requirement of numerous amplifiers and rectifiers in the power detector and high-resolution analog-to-digital converters, making them inefficient in terms of space usage.
Innovation Solution
A power-to-digital converter design that includes a power detector to extract most significant bits, reducing the need for high-resolution analog-to-digital converters and utilizing a timing control logic circuit to sequentially enable the power detector and ADC, resulting in a compact design with higher resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional power detector with multiple amplifiers and rectifiers is used, then the power detection function is achieved, but the silicon area occupied is large
Solution Approach 1:
The conversion process is divided into two sequential stages: first the power detector extracts MSBs during a first conversion period, then the ADC extracts LSBs during a second conversion period. This temporal segmentation allows each component to operate at lower resolution, reducing the silicon area required for both the power detector and ADC while maintaining overall high conversion precision.
2Measurement precision
If a high-resolution analog-to-digital converter is used, then the digital conversion precision is improved, but the device complexity and area increase
Solution Approach 1:
The digital code is segmented into MSBs extracted by the power detector and LSBs extracted by the ADC. By assigning different resolution requirements to different time periods and components, the ADC only needs to provide lower-resolution LSBs, significantly reducing its complexity and area while the overall precision is maintained through the combination of both extraction stages.
3Speed
If a conventional simultaneous conversion architecture is used, then the conversion speed is maintained, but the area consumption is large
Solution Approach 1:
The conversion process is divided into periodic stages: a first conversion period for MSB extraction by the power detector, followed by a second conversion period for LSB extraction by the ADC. The timing control logic circuit coordinates these periodic operations, enabling sequential processing that reduces area requirements while maintaining effective conversion throughput through structured time-multiplexed operation.
Data Source
AI summary
A power-to-digital converter (PDC) converting a signal power to digital code. The PDC comprises a power detector, an analog-to-digital converter (ADC), and a timing and logic control circuit. The power detector receives the signal power and generates a DC output and a first determined number of bits. The ADC is coupled to the power detector and receives and converts the DC output to a second determined number of bits. The timing control logic circuit is coupled to the power detector and the ADC and sequentially enables the power detector and the ADC. The first and second predetermined numbers of bits are respectively most significant bits (MSBs) and least significant bits (LSBs) of the digital code. The bit resolution of the digital code is the sum of the first and second numbers.