Split-Node Storage Circuit for FPGA Soft Error Mitigation
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Solution Overview
Problem
Integrated circuit devices, particularly field programmable gate arrays (FPGAs), face a high Soft Error Rate (SER) due to radiation-induced upsets from particles like cosmic neutrons and alpha particles, leading to unbalanced load between storage nodes in Master-Slave flip-flops, which increases the Failure In Time (FIT) rate.
Innovation Solution
The implementation of a split-node inverter arrangement in Master-Slave storage elements, where additional pass gates are used to balance the loading between storage nodes, mitigating Single-Event Upsets (SEUs) by equalizing the SEU cross-section for '0' and '1' inputs, and reducing the overall FIT rate with minimal latency penalty.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the Slave portion of a Master/Slave memory device is converted to DICE while keeping the Master portion as typical D-latch, then the overall FF FIT rate is reduced, but the Master D-latch has unbalanced load between the two storage nodes causing switching frequency difference
Solution Approach 1:
The patent applies local quality by making the inverter outputs asymmetric - one output drives a heavier load than the other. Specifically, one inverter output drives the Slave DICE cell while the other drives a lighter load, creating deliberately unbalanced loading that compensates for the inherent asymmetry in the Master-DICE/Master-D-latch configuration, thereby balancing the overall switching frequencies.
Solution Approach 2:
The patent employs asymmetry by intentionally creating unbalanced loading on the inverter outputs. Instead of symmetric loading, one side is designed with heavier loading to counterbalance the asymmetric nature of having one Master-DICE and one Master-D-latch, achieving frequency balance through controlled asymmetry.
2Reliability
If additional pass gates are added to balance loading, then the SEU cross-section is reduced, but the device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the inverter output into two separate outputs, each driving its own pass gate. This segmentation allows independent loading control on each path, enabling balanced loading that reduces SEU cross-section while maintaining manageable circuit complexity through modular organization.
Solution Approach 2:
The patent employs multi-functionality by using the same inverter structure to simultaneously achieve multiple goals: data inversion, load balancing, and SEU mitigation. The dual-output inverter configuration serves both as a logic inverter and as a load-balancing mechanism, reducing the need for additional dedicated components.
Data Source
AI summary
A circuit for storing data in an integrated circuit is described. The circuit comprises an inverter comprising a first transistor having a first gate configured to receive input data and a first output configured to generate a first inverted data output and a second transistor having a second gate configured to receive the input data and a second output configured to generate a second inverted data output; a first pass gate coupled to the first output of the inverter; a second pass gate coupled to the second output of the inverter; and a storage element having an input coupled to receive an output of the first pass gate and an output of the second pass gate. A method of storing data in an integrated circuit is also described.