Split Packet Transmission DMA Engine for Network Flow Processors
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Solution Overview
Problem
High-speed network flow processors typically do not buffer all packets, requiring efficient methods to merge and output packets from internal and external memory, especially for fast-path and exception packets.
Innovation Solution
A novel split packet transmission DMA engine that receives an egress packet descriptor to read and transfer the first and second parts of a packet information, using a compact packet number to locate the first part in internal memory and address information within the first part to locate the second part in external memory, assembling the packet information into a contiguous block for output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If packet information is split and stored in separate internal and external memory devices, then memory capacity is improved, but device complexity increases
Solution Approach 1:
The patent divides packet information into two parts: the first part (packet header and control information) is stored in internal memory of the network flow processor, while the second part (packet payload) is stored in external memory. This segmentation allows the system to leverage both fast internal memory for critical control data and high-capacity external memory for bulk data, resolving the contradiction between memory capacity and access speed.
Solution Approach 2:
The patent introduces a DMA (Direct Memory Access) engine as an intermediary device that automatically manages the merging of packet parts from internal and external memory. The DMA engine receives descriptors, retrieves packet parts from both memory locations, and assembles complete packets without processor intervention. This intermediary simplifies the complexity of coordinated memory access by providing a dedicated hardware mechanism for the merging operation.
2Ease of operation
If a processor is used to merge and output packet parts, then ease of operation is improved, but productivity decreases
Solution Approach 1:
The patent implements a self-service mechanism where the DMA engine autonomously performs the packet merging and output operations without requiring processor intervention. The DMA engine reads descriptors from memory, automatically retrieves packet parts from internal and external memory based on address information in the descriptors, merges them in the correct sequence, and outputs complete packets. This self-service approach eliminates the overhead of processor involvement in routine packet assembly tasks, thereby improving productivity while maintaining ease of operation through simple descriptor-based control.
Data Source
AI summary
Packet information is stored in split fashion such that a first part is stored in a first device and a second part is stored in a second device. A split packet transmission DMA engine receives an egress packet descriptor. The descriptor does not indicate where the second part is stored but contains information about the first part. Using this information, the DMA engine causes a part of the first part to be transferred from the first device to the DMA engine. Address information in the first part indicates where the second part is stored. The DMA engine uses the address information to cause the second part to be transferred from the second device to the DMA engine. When both the part of the first part and the second part are stored in the DMA engine, then the entire packet is transferred in ordered fashion to an egress device.