Split Packet Router for Time-Sensitive Networking Latency
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Solution Overview
Problem
Current network controller architectures prioritize high data throughput over low latency, leading to increased latency for time-critical packets due to inefficient packet routing and processing.
Innovation Solution
A split packet router architecture is introduced, comprising a priority-based router and a received packet router, which separates packet routing based on priority and writing packets to main memory, thereby reducing latency and area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a traditional packet router architecture is used to prioritize high data throughput, then network bandwidth utilization is improved, but latency for time-critical packets increases
Solution Approach 1:
The packet router is divided into two separate functional units: a priority router that handles time-critical packets with immediate forwarding based on priority markings, and a received packet router that processes standard packets through traditional queuing and buffering. This segmentation allows the system to simultaneously achieve low latency for priority packets and high throughput for overall network traffic by routing different packet types through optimized paths.
2Adaptability or versatility
If complex packet routing and processing is implemented to handle multiple traffic classes, then network functionality is improved, but area overhead increases
Solution Approach 1:
The routing functionality is segmented into two distinct paths: a simplified priority routing path that uses minimal processing based on packet priority markings to achieve fast forwarding, and a comprehensive received packet routing path that handles complex traffic classification, queuing, and buffering. This segmentation reduces area overhead by avoiding duplication of complex routing logic while maintaining adaptability for different traffic classes through the received packet router.
3Adaptability or versatility
If packets are buffered in memory for processing, then packet routing flexibility is improved, but latency for time-critical packets increases
Solution Approach 1:
The buffering architecture is segmented into two separate systems: a minimal buffering approach for priority packets that enables fast forwarding with minimal or no memory access, and a comprehensive buffering system for received packets that provides flexible queuing, scheduling, and retransmission capabilities. This segmentation allows time-critical packets to bypass memory buffering delays while maintaining routing flexibility for standard traffic through the buffered received packet path.
Data Source
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AI summary
A network interface device for implementing scheduling for time sensitive networking includes a network interface device comprising media access control (MAC) circuitry, including a priority router to parse a packet payload to determine a priority value; determine a corresponding traffic class based on the priority value from the packet payload; and route the packet payload to one of a plurality of traffic class-based packet buffers based on the traffic class; and a packet router to: retrieve a packet payload from the plurality of traffic class-based packet buffers based on the traffic class; and place the packet payload in a queue for a direct memory access (DMA) circuitry to store the packet payload in main memory.