Split-Parity ECC Copyback Across Mixed Code-Rate NAND Partitions

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Solution Overview

Problem

Memory devices face a mismatch in error correction data needs between SLC and QLC modes, leading to inefficient use of storage space and reduced endurance of SLC blocks due to higher stress and usage, resulting in increased error rates and reduced user data storage capacity.

Innovation Solution

Implementing a multi-layer code rate architecture that stores data using error correction with different code rates for different partitions, where SLC blocks use 20% parity data split into two parts, with one part stored within the partition and the other part available outside for higher error correction capability, while QLC blocks use 10% parity data, allowing for efficient copyback operations without wasting storage space.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If SLC blocks use higher error correction capability (20% parity data), then reliability is improved, but storage space is wasted and endurance is reduced

Engineering Contradiction:
Improveerror correction capabilityVSAvoidstorage space efficiency
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The 20% parity data for SLC blocks is segmented into two separate parts: first parity data stored within the SLC partition and second parity data stored in a separate location. This segmentation allows the system to maintain high error correction capability while enabling efficient copyback operations to QLC blocks, as only the user data and first parity data need to be copied, not the entire second parity data set.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The second part of the parity data (second parity data) is extracted from the SLC partition and stored separately in a different location within the memory device. This extraction allows QLC blocks to operate with only 10% parity data (first parity data) during copyback operations, improving storage space efficiency and reducing the over-provisioning penalty while maintaining the ability to provide full 20% error correction capability when needed.

Inventive Principle:
Principle #2Taking out (Extraction)

2Speed

If SLC blocks are used for incoming data, then write speed is improved, but endurance is reduced due to higher stress and usage

Engineering Contradiction:
Improvewrite speedVSAvoidendurance
Core Design Contradiction:
SpeedVSDuration of action of stationary object

Solution Approach 1:

The system performs preliminary error correction preparation by storing first parity data with the user data in SLC blocks before copyback operations. This preliminary action enables the SLC blocks to quickly prepare data for copyback to QLC blocks, maintaining high write speed while the separated second parity data structure reduces the stress on SLC blocks during repeated copyback operations, thereby improving endurance.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If copyback operations are performed without error correction, then productivity is improved, but data integrity is reduced

Engineering Contradiction:
Improvecopyback efficiencyVSAvoiddata integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The error correction data is segmented into first parity data (stored with user data in SLC) and second parity data (stored separately). During copyback operations, the system copies user data and first parity data together, maintaining data integrity for the copied portion while achieving high productivity. The second parity data remains in the SLC partition and can be used for additional error correction verification if needed, balancing both productivity and data integrity.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11829245B2Multi-layer code rate architecture for copyback between partitions with different code rates
Publication Date: 2023.11.28 MICRON TECHNOLOGY INC
  • US11829245B2 patent drawing
  • US11829245B2 patent drawing
  • US11829245B2 patent drawing

AI summary

Systems, methods, and apparatus related to a multi-level error correction architecture used for copying data in memory devices. In one approach, user data is stored in the first partition of a non-volatile memory. First error correction code data is generated for the user data and stored with the user data in the first partition. Second error correction code data is generated for the user data and stored outside the first partition. The second error correction code data provides an increased error correcting capability that is compatible with the error correction algorithm used with the first error correction code data. A copyback operation is used to copy the user data and the first error correction code, but not the second error correction code, to a second partition of the non-volatile memory. The second error correction code can be selectively used if there is a need to recover portions of the user data stored in the first partition.