Split Partitioning Power Converter for EMI Reduction
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Solution Overview
Problem
Existing system-in-package (SiP) power converters face inefficiencies and increased complexity due to separate dies for power switches and control logic, leading to larger size, higher cost, and susceptibility to electromagnetic interference, while monolithic integration compromises efficiency for accuracy.
Innovation Solution
A SiP power converter design with power switches and driver/control logic distributed across two dies, where high-efficiency FET or SFET type switches are on one die and CMOS type switches and feedback control circuitry on another, allowing for accurate current sensing without charge pumps and reduced noise interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power switches and control logic are integrated on separate dies, then efficiency is improved, but device complexity and package size increase
Solution Approach 1:
The power converter is divided into two separate dies: a first die containing high-efficiency FET or SFET power switches, and a second die containing CMOS control logic and feedback circuitry. This segmentation allows each die to be optimized for its specific function, maintaining high efficiency while enabling accurate control.
Solution Approach 2:
The patent combines the FET/SFET power switches and CMOS control logic into a single system-in-package (SiP) module, merging the benefits of high-efficiency power switching with accurate CMOS control in an integrated package that manages complexity through unified packaging.
2Measurement precision
If feedback control circuitry is placed on a separate die from power switches, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The feedback control circuitry and current sensing circuitry are extracted from the power switch die and placed on a separate CMOS die. This extraction isolates the sensitive measurement circuits from the high-power switching nodes, improving current sensing accuracy by eliminating electromagnetic interference while managing complexity through functional separation.
3Device complexity
If all components are integrated on a single die, then device complexity is reduced, but efficiency decreases
Solution Approach 1:
Different regions of the system (first die and second die) are assigned different qualities and optimizations: the first die uses high-efficiency FET or SFET technology for power switching, while the second die uses CMOS technology for control and sensing. This local quality differentiation ensures high efficiency in power conversion while maintaining accurate control, avoiding the efficiency losses of monolithic integration.
Data Source
AI summary
A power converter is described that includes components arranged within a first die and a second die of a single package. The first die includes one or more first switches coupled to a switching node of a power stage. The second die includes one or more second switches coupled to the switching node of the power stage, a feedback control unit configured to detect a current level at the one or more second switches of the power stage, and a controller unit configured to control the one or more first switches and the one or more second switches of the power stage based at least in part on the current level detected by the feedback control unit.