Split-Path Equalizer for High-Speed CDR Timing Recovery
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Solution Overview
Problem
Current clock and data recovery (CDR) circuits face challenges in accurately recovering timing information at high signaling rates, as existing equalization techniques are not effectively helpful for clock recovery and can result in higher bit-error rates and clock jitter.
Innovation Solution
The implementation of a split-path equalizer that applies independent equalization settings to data and edge sampling paths, allowing for more precise clock recovery and lower bit-error rates, particularly at high signaling rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional equalization techniques are used in CDR circuits, then data recovery can be achieved, but clock recovery accuracy deteriorates resulting in higher bit-error rates and clock jitter
Solution Approach 1:
The equalization function is segmented into two independent paths: one for data sampling and one for edge sampling. Each path has its own equalization circuit with independently adjustable settings, allowing optimization for各自的 function without compromising the other
Solution Approach 2:
Different equalization settings are applied to different parts of the system: the data path uses settings optimized for data recovery while the edge path uses settings optimized for clock recovery, allowing each part to have the quality it needs
2Speed
If high signaling rates are used, then data transmission speed is improved, but equalization effectiveness deteriorates leading to higher bit-error rates
Solution Approach 1:
The equalization settings are made dynamically adjustable and independently controllable for each path, allowing the system to adapt to high signaling rates by optimizing the edge path settings for accurate timing recovery at these speeds
3Device complexity
If single equalization settings are used for both data and edge sampling, then device complexity is reduced, but performance deteriorates due to inability to optimize both paths simultaneously
Solution Approach 1:
The equalization system is divided into separate circuits for data and edge paths, allowing independent optimization of each path's performance without compromising the other
Data Source
AI summary
This disclosure provides a split-path equalizer and a clock recovery circuit. More particularly, clock recovery operation is enhanced, particularly at high-signaling rates, by separately equalizing each of a data path and an edge path. In specific embodiments, the data path is equalized in a manner that maximizes signal-to-noise ratio and the edge path is equalized in a manner that emphasizes symmetric edge response for a single unit interval and zero edge response for other unit intervals (e.g., irrespective of peak voltage margin). Such equalization tightens edge grouping and thus enhances clock recovery, while at the same time optimizing data-path sampling. Techniques are also disclosed for addressing split-path equalization-induced skew.