Split-Path Equalizer for High-Rate Clock Recovery
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Solution Overview
Problem
Current clock and data recovery techniques face challenges in accurately recovering timing information at high signaling rates, as existing equalization methods are not effectively helpful for clock recovery and often result in higher bit-error rates and increased jitter.
Innovation Solution
A split-path equalizer is introduced, which applies independent equalization parameters to data and edge-sampling paths, using continuous-time linear equalizers and decision feedback equalization techniques to optimize signal recovery and compensate for skew, thereby enhancing clock recovery accuracy and reducing bit-error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional equalization methods are used for clock recovery at high signaling rates, then signal processing is simplified, but clock recovery accuracy deteriorates and bit-error rates increase
Solution Approach 1:
The equalization process is divided into two separate paths: a data path and an edge path. Each path has its own independent equalizer with separately optimized parameters. The data path equalizer is optimized for data sampling while the edge path equalizer is optimized for edge sampling, allowing each to be tuned independently for its specific function without compromising the other.
Solution Approach 2:
Different equalization parameters are applied to different parts of the signal processing system. The data path uses equalization parameters optimized for maximizing data sampling accuracy, while the edge path uses different parameters optimized for edge sampling. This allows each path to have locally optimized quality appropriate to its specific function.
2Measurement precision
If single equalization settings are used for both data and edge sampling paths, then device complexity is reduced, but clock recovery accuracy and timing precision deteriorate
Solution Approach 1:
The equalization system is segmented into two independent subsystems: a data path equalizer and an edge path equalizer. Each subsystem can be independently configured and optimized, allowing complex equalization functionality to be achieved while maintaining modular architecture that simplifies design and implementation.
Solution Approach 2:
The split-path equalizer architecture provides multi-functionality by serving two distinct purposes: data sampling optimization and edge sampling optimization. Both functions are achieved through a unified equalization framework that processes the same input signal through two separately optimized paths, eliminating the need for additional hardware.
3Measurement precision
If conventional equalization is applied to both data and edge paths with same parameters, then ease of operation is maintained, but skew compensation capability is lost
Solution Approach 1:
Different equalization parameters are applied to the data path and edge path to account for their different functional requirements. The data path parameters are optimized for data sampling while edge path parameters are optimized for edge detection and timing recovery. This local optimization enables effective skew compensation while maintaining independent configurability of each path.
Solution Approach 2:
The system employs different sets of equalization parameters for the two paths. By changing the parameters independently for each path, the system can optimize performance for both data sampling and edge sampling simultaneously, enabling effective skew compensation without requiring complex manual configuration.
Data Source
AI summary
This disclosure provides a split-path equalizer and a clock recovery circuit. More particularly, clock recovery operation is enhanced, particularly at high-signaling rates, by separately equalizing each of a data path and an edge path. In specific embodiments, the data path is equalized in a manner that maximizes signal-to-noise ratio and the edge path is equalized in a manner that emphasizes symmetric edge response for a single unit interval and zero edge response for other unit intervals (e.g., irrespective of peak voltage margin). Such equalization tightens edge grouping and thus enhances clock recovery, while at the same time optimizing data-path sampling. Techniques are also disclosed for addressing split-path equalization-induced skew.