3D Memory Structure With Split Peripheral Circuits for Higher Density
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Solution Overview
Problem
Planar memory cells face density limitations and scaling challenges due to the increasing complexity and cost of peripheral circuits, which are not effectively addressed by traditional scaling methods, and the high voltage requirements of 3D NAND Flash memory devices complicate further size reduction.
Innovation Solution
The peripheral circuits are disposed in different vertical planes, with the memory cell array and high-voltage peripheral circuits stacked over low-voltage circuits, using hybrid or transfer bonding to reduce planar chip size and increase memory density, while allowing independent thermal budgets and interconnect materials for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology and fabrication process, then memory density is improved, but feature sizes approach a lower limit making planar process and fabrication techniques challenging and costly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional stacked architecture. Multiple memory cell arrays are stacked vertically and bonded together, utilizing the third dimension (vertical stacking) to increase memory density without further reducing feature sizes in the planar direction. This resolves the contradiction by achieving higher density through dimensional transition rather than continued scaling.
2Adaptability or versatility
If peripheral circuits are integrated with memory cell arrays in planar architecture, then device functionality is improved, but the increasing complexity and size of peripheral circuits limit further memory density improvement
Solution Approach 1:
The patent segments the memory device into distinct stacked layers: memory cell arrays are placed in first and second semiconductor structures, while peripheral circuits are separated into different regions. The memory cell arrays can be positioned away from peripheral circuits in the stacked architecture, allowing independent optimization of each component without the planar layout constraints that previously forced peripheral circuits to encroach on memory array space.
Solution Approach 2:
By stacking memory cell arrays vertically above or beside peripheral circuits in the third dimension, the patent enables both high-density memory arrays and fully-functional peripheral circuits to coexist without competing for planar space. This vertical separation resolves the contradiction between maintaining device functionality and maximizing memory density.
3Quantity of substance
If 3D NAND Flash memory devices are used to address density limitations, then memory density is improved, but high voltage requirements complicate further size reduction
Solution Approach 1:
The patent divides peripheral circuits into multiple semiconductor structures stacked separately from memory cell arrays. This segmentation allows different voltage domains to be isolated in different stacked layers, with voltage management circuits positioned adjacent to the memory arrays they serve. This reduces the complexity of distributing high voltages throughout the device while maintaining high density.
Data Source
AI summary
A three-dimensional (3D) memory device includes a first, a second, and a third semiconductor structures. The first semiconductor structure includes a first semiconductor layer and an array of memory strings over the first semiconductor layer. The second semiconductor structure includes a second semiconductor layer and a first peripheral circuit over the second semiconductor layer, the first peripheral circuit including a first transistor. The third semiconductor structure includes a third semiconductor layer and a second peripheral circuit over the third semiconductor layer, the second peripheral circuit including a second transistor. The first semiconductor structure is between the second semiconductor structure and the third semiconductor structure. A thickness of the second semiconductor layer is different from a thickness of the third semiconductor layer.