Split Pillar Memory Architecture for High Density

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Solution Overview

Problem

Existing memory devices face challenges in increasing memory cell density, reducing power consumption, and decreasing manufacturing costs while maintaining reliable data storage and retrieval.

Innovation Solution

The implementation of split pillar architectures for memory devices, which involve an arrangement of conductive contacts and alternating layers of conductive and insulative materials, allowing for a tighter spacing between memory cells while maintaining dielectric thickness to sustain voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If traditional memory device architectures are used, then manufacturing processes are simpler, but memory cell density is lower

Engineering Contradiction:
Improvememory cell densityVSAvoidarchitecture complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The pillar structure is divided into multiple segments with different materials along the vertical axis. Each segment serves a specific function: charge trapping layer for data storage, tunnel barrier for electron confinement, and blocking layer for current direction control. This segmentation enables higher density while maintaining manufacturability through standardized layer deposition processes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from planar 2D memory architecture to 3D vertical architecture by stacking multiple functional layers vertically. This dimensional change allows memory cells to be arranged in three dimensions, significantly increasing storage density without proportionally increasing manufacturing complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If spacing between memory cells is reduced to increase density, then manufacturing precision requirements increase, but if spacing is maintained, then device area increases

Engineering Contradiction:
Improvememory cell densityVSAvoidspacing precision
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent changes the critical dimension parameter from lateral spacing to vertical stacking. By utilizing the vertical dimension for multiple memory cell layers, the lateral spacing between cells can be reduced without proportionally reducing the dielectric thickness, thus maintaining electrical isolation while increasing density.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The use of composite material structures with alternating conductive and insulative layers provides mechanical support and electrical isolation. The insulative layers act as natural spacers that maintain precise spacing between conductive elements, reducing the need for high-precision lateral positioning during manufacturing.

Inventive Principle:
Principle #40Composite materials

3Reliability

If dielectric thickness is increased to maintain voltage sustainment, then spacing between memory cells increases, but if spacing is reduced, then voltage isolation reliability decreases

Engineering Contradiction:
Improvevoltage isolationVSAvoidmemory cell density
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The dielectric isolation function is segmented into multiple thin insulative layers distributed vertically throughout the structure. Each insulative layer contributes to the overall voltage sustainment capability, allowing the cumulative isolation performance to match or exceed that of a single thick dielectric layer while enabling tighter cell spacing.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The alternating stack of conductive and insulative materials creates a composite structure where insulative layers provide both mechanical spacing and electrical isolation. This composite approach allows optimized balance between cell density and voltage isolation by adjusting the thickness and material properties of individual insulative layers.

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS20250107105A1Split pillar architectures for memory devices
Publication Date: 2025.03.27 MICRON TECHNOLOGY INC
  • US20250107105A1 patent drawing
  • US20250107105A1 patent drawing
  • US20250107105A1 patent drawing

AI summary

Methods, systems, and devices for split pillar architectures for memory devices are described. A memory device may include a substrate arranged with conductive contacts in a pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, an insulative material may be deposited in a trench. Portions of the insulative material may be removed to form openings, into which cell material is deposited. Conductive pillars may extend perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. The conductive pillars may be divided to form first and second pillars.