Split Power Switch for SRAM Write Stability
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Solution Overview
Problem
Existing SRAM cell designs face challenges in balancing stability and writeability, as robustness for stability often hinders write operations and weakening for writeability compromises stability, especially under varying voltage and temperature conditions.
Innovation Solution
Implementing a split power switch circuit that selectively adjusts power levels to SRAM cells during write operations, allowing one side to drop while maintaining the other side at a reference voltage, thereby reducing the minimum voltage required for writing and ensuring stable logic state regeneration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If robust cross-coupled logic gates are implemented to improve stability, then stability is improved, but writeability deteriorates
Solution Approach 1:
The patent applies dynamics by making the power supply voltage to the cross-coupled logic gates time-varying rather than static. During normal operation, full voltage is provided for stability, but during write operations, the voltage is dynamically reduced to improve writeability. This temporal dynamic adjustment resolves the contradiction between stability and writeability.
Solution Approach 2:
The patent changes the voltage parameter of the power supply to the cross-coupled logic gates based on operational mode. By adjusting the voltage level - maintaining it at nominal levels for stability during reads and reducing it during writes - the system optimizes both stability and writeability at different times, resolving the inherent trade-off.
2Ease of operation
If cross-coupled logic gates are weakened to improve writeability, then writeability is improved, but stability deteriorates
Solution Approach 1:
Rather than permanently weakening the logic gates, the patent dynamically adjusts their effective strength by modulating the power supply voltage. The gates maintain full strength during normal operation for stability, and are temporarily weakened only during write operations by reducing voltage, thus achieving both goals without compromise.
3Ease of operation
If a single power switch is used to reduce voltage during write operations, then writeability is improved, but logic state regeneration deteriorates
Solution Approach 1:
The patent segments the power supply control into separate switches for each cross-coupled logic gate rather than using a single shared power switch. This allows independent control of power to each gate, enabling one gate to be weakened for writing while the other maintains full power for proper logic state regeneration, thus resolving the contradiction.
Solution Approach 2:
The patent applies different power levels to different parts of the circuit - specifically, different power levels to the two cross-coupled logic gates. During write operations, one gate receives reduced power to facilitate writing, while the other receives full power to ensure proper regeneration, creating local quality differences that resolve the contradiction.
Data Source
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AI summary
An approach to selectively powering a memory device is provided to improve the writeability of static random access memory (SRAM) cells without adversely compromising their stability. For example, various split power switch circuits and methods are used to permit the voltage or current of a power supply line connected with one side of an SRAM cell to drop during write operations. This drop weakens one side of the SRAM cell and reduces the drive-fight between transistors of the SRAM cell and external write circuitry. As a result, the minimum voltage for writing new logic states into the SRAM cell is reduced to permit overall lower operating voltages for the SRAM cell and related circuitry. By continuing to maintain a second side of the SRAM cell at the reference voltage or current, the SRAM cell can successfully switch to a newly written logic state.