Split PP/NN Cell Layout for Direct Abutment and Higher Logic Density
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Solution Overview
Problem
Traditional standard cell structures and PPNN cell structures have size differences that prevent direct abutment, leading to a loss of circuit area and reduced logic density in integrated circuits due to buffer area requirements and gate shorting issues.
Innovation Solution
A split PP/NN cell structure is introduced, which has the same size as PPNN cell structures, includes more logic gates and functions, and is designed to directly abut PPNN cell structures without a buffer area, utilizing fly metal-over-diffusion contacts electrically insulated from oxide diffusion areas to increase logic density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PPNN cell structures with larger oxide diffusion areas are used, then logic gate performance is improved, but logic density is reduced
Solution Approach 1:
The cell structure is divided into two separate cells (first cell and second cell) that can be independently designed and optimized. Each cell contains its own oxide diffusion areas and logic gates, allowing the larger OD areas to be distributed across multiple cells rather than concentrated in one cell, thereby maintaining performance while improving overall density.
Solution Approach 2:
The invention extends the cell structure in the first direction by creating adjacent first and second cells. This dimensional extension allows multiple high-performance logic gates with large oxide diffusion areas to be packed into a larger total area, improving logic density while maintaining the performance benefits of large OD areas in each individual gate.
2Area of stationary object
If PPNN cell structures are placed adjacent to traditional standard cell structures, then circuit area is reduced, but gate shorting occurs
Solution Approach 1:
The gate contact structure is made non-uniform by extending it beyond the oxide diffusion area on one side while terminating before the oxide diffusion area on the other side. This asymmetric configuration allows adjacent cells to be placed closer together without causing gate shorting, as the gate contact selectively connects to only the intended oxide diffusion area while leaving clearance to adjacent structures.
3Reliability
If buffer areas are inserted between PPNN and traditional standard cell structures, then gate shorting is prevented, but logic density is reduced
Solution Approach 1:
The gate contact dimensions and positioning are modified to extend beyond the oxide diffusion area boundary on the side adjacent to traditional standard cells. This parameter change in gate contact geometry allows direct abutment of different cell types without requiring buffer areas, as the extended gate contact maintains proper electrical isolation while maximizing space utilization.
Data Source
AI summary
An integrated circuit including a first cell and a second cell. The first cell includes a first plurality of active areas that extend in a first direction and a first plurality of gates that extend in a second direction that crosses the first direction, the first cell having first cell edges defined by breaks in the first plurality of gates. The second cell includes a second plurality of active areas that extend in the first direction and a second plurality of gates that extend in the second direction, the second cell having second cell edges defined by breaks in the second plurality of gates. Each of the second plurality of active areas is larger than each of the first plurality of active areas and the first cell is adjacent the second cell such that the first cell edges align with the second cell edges.