Split-Radix DGT Cryptosystem Processor for Lattice-Based Polynomial Multiplication
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Solution Overview
Problem
Current cryptography methods, particularly in lattice-based cryptography, face challenges in reducing computing complexity for polynomial multiplication, which is a bottleneck in post-quantum cryptography implementations.
Innovation Solution
A cryptosystem processor is designed to perform split-radix Discrete Galois Transformation (DGT) and inverse DGT, utilizing a twiddle factor memory, SRDGT butterfly units, and a stream permutation network to achieve lower computing complexity and efficient data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional NTT algorithms are used for polynomial multiplication in lattice-based cryptography, then the transformation can be performed, but the computing complexity is high
Solution Approach 1:
The patent applies segmentation by dividing the polynomial multiplication process into distinct modular components: NTT transformation, component-wise multiplication, and inverse NTT transformation. Each module is independently optimized and can be processed separately, reducing overall computing complexity while maintaining efficiency.
Solution Approach 2:
The patent changes parameters by optimizing the NTT algorithm implementation with specific parameter selections for the transformation, using efficient modular arithmetic operations, and adjusting the computational parameters to minimize complexity while preserving the required cryptographic security levels.
2Loss of time
If polynomial multiplication is performed directly without transformation, then the operation is straightforward, but the computing time is excessive
Solution Approach 1:
The patent applies preliminary action by performing the NTT transformation on the input polynomials before multiplication. This pre-processing step converts the polynomials into a form that enables faster component-wise multiplication, significantly reducing the overall computation time despite the added transformation complexity.
Solution Approach 2:
The patent substitutes the direct polynomial multiplication mechanism with a transformed approach using NTT. Instead of performing complex polynomial multiplication directly, the system uses the properties of the NTT transformation to convert the operation into simpler component-wise multiplication in the transformed domain, achieving faster computation.
3Speed
If hardware accelerators are used for polynomial multiplication, then the computing speed improves, but the device complexity and cost increase
Solution Approach 1:
The patent applies universality by designing a hardware architecture that can perform multiple cryptographic operations using the same NTT-based polynomial multiplication engine. The same computational units are reused across different cryptographic primitives, reducing overall hardware complexity while maintaining high computation speed for polynomial operations.
Data Source
AI summary
A cryptosystem processor includes a twiddle factor memory, a SRDGT BFU, and a SPN. The twiddle factor memory has ZETA ports. The at least one SRDGT BFU has six input ports and four output ports and switchable among operation in DGT/IDGT/CWM mode, in which two of the input ports electrically communicate with the ZETA ports, respectively. The SRDGT BFU is configured to read and write two data points when working under the DGT/IDGT mode and is configured to read and write four data points when working under the CWM mode. The SPN electrically communicates with the SRDGT BFU and has at least one dual-port BRAM serving as memory cache configured to store polynomial, in which the SPN is configured to support the required number of data points reading or writing per cycle in the DGT/IDGT/CWM mode.