Split-Rail Level Shifter Topology for Isolated Power Control
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Solution Overview
Problem
Existing split rail power supply solutions increase cost, power consumption, and design area due to additional analog PMU circuitry and external components, leading to inefficiencies in power management and latency.
Innovation Solution
A level shifter circuit topology using cross-coupled PMOS and NMOS transistors with a capacitor, which stabilizes power transitions and reduces the need for additional PMU circuitry, enhancing isolation and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple instances of PMU circuitry are included for each power supply, then power control reliability is improved, but device complexity and cost increase
Solution Approach 1:
A single PMU circuit is designed to control multiple power supplies (VDDIO1, VDDIO2, VDDIO3) through a standardized interface. The PMU uses a binary-coded control signal on the GPIO pin to selectively enable or disable different power supplies, making the power management system universal and reducing the need for multiple dedicated PMU instances.
Solution Approach 2:
A level shifter circuit is introduced as an intermediary between the GPIO pin and the power supply control nodes. This level shifter translates the control signal to appropriate voltage levels for each power supply and provides isolation, allowing a single PMU to safely control multiple power supplies without direct complex interconnections.
2Manufacturing precision
If external power management circuitry with dedicated GPIO pin is used, then power control precision is improved, but device complexity and pin count increase
Solution Approach 1:
The level shifter circuit is integrated within the PMU block rather than being external. This merging of functions allows the PMU to directly control multiple power supplies with precise timing and voltage levels while using existing GPIO infrastructure, reducing external components and maintaining control precision.
3Adaptability or versatility
If additional analog PMU circuitry is added, then power management capability is improved, but area requirements increase
Solution Approach 1:
The PMU is designed as a universal power management unit that can control any number of power supplies through a single GPIO interface. This multi-functional design eliminates the need for separate analog PMU circuitry for each power supply, significantly reducing the overall area required while maintaining full adaptability.
Solution Approach 2:
The system uses existing digital GPIO infrastructure and standard level shifting techniques rather than adding dedicated analog PMU blocks. This self-service approach leverages available resources to provide comprehensive power management capability without increasing area.
4Reliability
If daisy-chained LDOs are used for split rail support, then power control reliability is improved, but pin count and external components increase
Solution Approach 1:
The level shifting and isolation functions are extracted from external components and implemented as integrated circuits within the PMU. This extraction eliminates the need for external level shifters and daisy-chained LDO configurations, reducing pin count and external components while maintaining reliable power control.
Data Source
AI summary
Embodiments disclosed herein relate to split rail architecture for power supplies in a system, and more particularly, to providing isolation and control of a power supply. In an example, an integrated circuit device is provided that includes a device voltage supply, an input/output (I/O) voltage supply coupled to the device voltage supply, and a level shifter circuit coupled to the I/O voltage supply. The level shifter circuit includes a pair of cross-coupled p-type metal-oxide semiconductor field effect transistors (PMOS transistors), a pair of n-type transistors (NMOS transistors) coupled between the pair of cross-coupled PMOS transistors and a ground connection, and an inverter circuit coupled to the device voltage supply and the level shifter circuit. The level shifter circuit further includes a capacitor coupled to the pair of cross-coupled PMOS transistors and the ground connection and is in parallel with respect to a first one of the pair of NMOS transistors.