Split Rail Output Buffer for High Slew Rate Display Driving
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Solution Overview
Problem
Display driving devices face challenges in achieving high slew rates without increasing current consumption, especially as load capacitance increases and horizontal period decreases, requiring fast slewing times and low power consumption.
Innovation Solution
The implementation of a split rail-to-rail output buffer with feedback circuits and cascode current mirrors in a display driving device, which includes two output buffers connected between different voltage rails and feedback loops to manage source line driving signals, allowing for high slew rates without increasing current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If load capacitance increases and horizontal period decreases, then display resolution and refresh rate improve, but slew rate requirement increases and current consumption increases
Solution Approach 1:
The output buffer is divided into two separate output buffers (first output buffer and second output buffer), each operating between different voltage rails (first voltage rail-second voltage rail and third voltage rail-fourth voltage rail). This segmentation allows independent optimization of each buffer's performance to achieve high slew rates without proportionally increasing overall current consumption.
Solution Approach 2:
Feedback circuits are introduced to connect the output terminals of both output buffers to their respective negative input terminals. These feedback mechanisms enable the output buffers to automatically adjust their operation, maintaining high slew rates while optimizing current consumption by reducing idle current flow.
2Speed
If output buffer operates between voltage rails, then slew rate improves, but power consumption increases
Solution Approach 1:
The voltage supply is segmented into four distinct voltage rails (first voltage rail, second voltage rail, third voltage rail, fourth voltage rail), with each output buffer operating between a specific pair of rails. This segmentation enables optimized voltage delivery for high slew rate operation while minimizing unnecessary power consumption by isolating the operational voltage domains.
Solution Approach 2:
Feedback circuits connect output terminals to negative input terminals of the respective output buffers, creating automatic voltage regulation. This feedback mechanism ensures that power is consumed only when needed for signal transitions, maintaining high slew rates while reducing idle power consumption.
3Speed
If traditional output buffer used, then circuit simplicity maintained, but slew rate insufficient and settling time long
Solution Approach 1:
The traditional single output buffer is segmented into two parallel output buffers, each capable of driving multiple source lines simultaneously. This segmentation doubles the effective driving capability, reducing slewing times and improving settling speed despite the increased structural complexity.
Solution Approach 2:
Each output buffer is designed with multi-functionality, where the first output buffer can drive first source lines and the second output buffer can drive second source lines, with both buffers capable of operating in different voltage domains. This universal design enables flexible configuration to achieve fast slewing without requiring a completely new circuit architecture.
Data Source
AI summary
An output buffer having a high slew rate, a method of controlling the output buffer, and a display driving device including the output buffer. The output buffer includes: a first output buffer adapted to output a source line driving signal to a first output terminal in response to a first control signal and output a source driving signal to a second output terminal in response to a second control signal; a second output buffer adapted to output a source line driving signal to a third output terminal in response to the first control signal and output a source line driving signal to a fourth output terminal in response to the second control signal; and a feedback circuit for connecting the first through fourth output terminals to negative input terminals of the first and second output buffers in response to the first control signal and the second control signal.