Split-Reference SAR ADC for Faster Low-Noise Conversion

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Solution Overview

Problem

Analog-to-digital converters (ADCs) face challenges in achieving low noise figures and high conversion speeds due to the use of external voltage references, which limit their performance in microcontroller applications, especially when requiring simultaneous sampling of multiple analog inputs with precise timing.

Innovation Solution

The implementation of a split-reference successive-approximation ADC circuit using both external and internal references allows for lower-bit conversion speed exploitation and low noise figure benefits, with MSB capacitors connected to an external reference and LSB capacitors to a ground or internal reference, optimizing noise-versus-speed performance and reducing circuit size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If an external voltage reference is used to achieve low noise figure, then noise performance is improved, but conversion speed is limited due to bond wire inductance

Engineering Contradiction:

Improvenoise figureVSAvoidconversion speed

Core Design Contradiction:

Object-affected harmful factorsVSSpeed

Solution Approach 1:

The patent divides the capacitor array into two separate arrays: a first capacitor array connected to the external high-voltage reference and a second capacitor array connected to the internal low-voltage reference. This segmentation allows the ADC to exploit the low noise figure of the external reference for MSB conversion while using the fast internal reference for LSB conversion, thereby resolving the speed-noise tradeoff.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different parts of the capacitor array are assigned different reference voltages based on their significance. The MSB capacitors use the external reference for low noise, while the LSB capacitors use the internal reference for high speed. This local differentiation optimizes the overall ADC performance by matching each capacitor group's reference to its specific requirements.

Inventive Principle:

Principle #3Local quality

2Adaptability or versatility

If a 5V external reference is used for ratiometric measurement, then measurement capability is improved, but transistor speed decreases due to higher voltage operation

Engineering Contradiction:

Improveratiometric measurement capabilityVSAvoidtransistor switching speed

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent segments the voltage reference system into two parts: an external 5V reference for ratiometric measurements and an internal 1V reference for fast digital operation. The capacitor array is similarly segmented, with MSB capacitors connected to the 5V reference and LSB capacitors connected to the 1V reference, enabling both measurement capabilities and high-speed operation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The internal low-voltage reference acts as an intermediary between the external high-voltage reference and the digital core circuitry. It enables fast transistor operation while the external reference provides the ratiometric measurement capability, thus mediating between conflicting voltage requirements.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Speed

If an internal reference buffer is used to enable fast ADC operation, then conversion speed is improved, but power consumption and noise increase

Engineering Contradiction:

Improveconversion speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

Instead of using a full-power internal reference buffer for all capacitors, the patent applies the internal reference only partially to the LSB capacitor array. This partial action reduces the power consumption and noise contribution of the reference buffer while still enabling fast operation where it matters most for achieving high conversion speed.

Inventive Principle:

Principle #16Partial or excessive action

4Speed

If digital transistors are used to increase ADC speed, then conversion speed is improved, but noise figure increases

Engineering Contradiction:

Improveconversion speedVSAvoidnoise figure

Core Design Contradiction:

SpeedVSObject-affected harmful factors

Solution Approach 1:

The patent segments the conversion process into two phases: MSB conversion using external reference with slower but lower-noise transistors, and LSB conversion using internal reference with faster but higher-noise transistors. This segmentation allows digital transistors to be used only where speed is critical while maintaining low noise figure for the majority of the conversion.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS11700006B2Passive sample-and-hold analog-to-digital converter with split reference voltage

Publication Date: 2023.07.11 INFINEON TECHNOLOGIES AG

AI summary

An analog-to-digital converter (ADC) circuit comprises one or more most-significant-bit (MSB) capacitors having first ends connected to a voltage comparator and one or more least-significant-bit (LSB) capacitors having first ends connected to the comparator. The circuit further comprises a first switching circuit for each MSB capacitor, configured to selectively connect the second end of the respective MSB capacitor to (a) an input voltage, for sampling, (b) a ground reference, during portions of a conversion phase, and (c) a first conversion reference voltage, for other portions of the conversion phase. The circuit still further comprises a second switch circuit, for each LSB capacitor, configured to selectively connect the second end of the respective LSB capacitor between (d) the ground reference, during portions of the conversion phase, and (e) a second conversion reference voltage, for other portions of the conversion phase, the second conversion reference voltage differing from the first.