Split Replacement Metal Gate Integration for FinFET Reliability
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Solution Overview
Problem
The integration of replacement metal gate (RMG) modules in semiconductor device formation faces challenges due to high temperature steps that can degrade the metal work function, particularly in gate last flows where the source/drain activation anneal is performed at temperatures above 550°C, affecting the thermal budget and reliability of the gate stack.
Innovation Solution
The RMG integration is split into two modules, with the first module comprising high temperature steps performed before epitaxial growth and the second module conducted after growth, avoiding exposure of the work function metal to high temperatures by using a sacrificial plug and depositing the work function metal between spacers post-epitaxial growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the replacement metal gate module is implemented as last with reliability anneal at 850-900°C, then the gate stack undergoes high temperature processing, but the metal work function degrades due to excessive thermal exposure
Solution Approach 1:
The replacement metal gate module is divided into two separate modules: the first module performs high-k material deposition and annealing before epitaxial growth, while the second module performs work function metal deposition after epitaxial growth. This segmentation allows high temperature steps to be isolated to the first module, protecting the temperature-sensitive work function metal in the second module from thermal degradation.
Solution Approach 2:
The first replacement metal gate module is performed preliminarily before epitaxial growth, completing all high temperature processing steps for the high-k material in advance. This preliminary action ensures that when the work function metal is deposited in the second module afterward, it is not exposed to subsequent high temperature steps that would cause work function degradation.
2Reliability
If the source/drain doping activation anneal is performed at temperatures above 550°C, then the doping activation is effective, but the metal work function is adversely affected
Solution Approach 1:
The process is segmented so that source/drain doping activation anneal is performed in the first replacement metal gate module before the work function metal is deposited. This ensures that the metal work function remains below 550°C during doping activation, preventing work function degradation while still achieving effective doping activation.
3Ease of manufacture
If the RMG module is implemented as last, then the gate stack is formed after epitaxial growth, but additional high temperature anneal steps are required after gate stack deposition
Solution Approach 1:
The replacement metal gate module is segmented into two parts with epitaxial growth occurring between them. The first module is completed before epitaxial growth, and the second module is completed after epitaxial growth without requiring high temperature steps. This eliminates the need for high temperature anneal steps after gate stack deposition while maintaining ease of manufacture.
4Productivity
If the work function metal is deposited before epitaxial growth, then the gate stack is complete early, but the work function metal is exposed to high temperatures during subsequent processing
Solution Approach 1:
The sequence is inverted from the conventional approach: instead of depositing the work function metal before epitaxial growth and subsequent high temperature steps, the work function metal is deposited after epitaxial growth is complete. This inversion ensures that the work function metal is not exposed to high temperatures during epitaxial growth or doping activation anneal, preserving its thermal stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents degradation of the gate stack, allows for an epitaxial growth last scheme without high thermal exposure, and reduces the complexity of high-k metal gate recess and metal gate cut, enabling more options for the gate plug and epitaxial growth.
Implementation Method 1
providing high-k material on at least one of the one or more fins or on one or more nanowires formed from the one or more fins
Implementation Method 2
providing high-k material on at least one of the one or more fins or on one or more nanowires formed from the one or more fins
Implementation Method 3
a work function metal is deposited between at least part of the spacers such that the work function metal is covering the high-k material
Implementation Method 4
Epitaxially growing a source and a drain in the one or more fins or in the one or more nanowires
Implementation Method 5
Epitaxially growing a source and a drain in the one or more fins or in the one or more nanowires
Implementation Method 6
followed by one or more annealing steps
Implementation Method 7
one or more annealing steps
Data Source
AI summary
A method for forming a semiconductor device, the method including: providing a substrate with at least one fin or nanowire; forming a dummy gate; providing spacers on the at least one fin or nanowire and the dummy gate; performing a first RMG module wherein high-k material is provided on at least one fin or nanowire, between the spacers; one or more annealing steps; providing a sacrificial plug between the spacers; epitaxially growing a source and drain in the at least one fin or nanowire; removing the sacrificial plug; performing a second RMG module wherein a WFM is deposited between at least part of the spacers such that the WFM is covering the high-k material of the at least one fin or nanowire.