Split SAR ADC Non-Linearity Reduction via Inverted Reset
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Solution Overview
Problem
Split-SAR analog-to-digital converters in image sensors introduce differential non-linearity (DNL) errors due to parasitic capacitance, leading to undesired visual artifacts, especially in low light conditions, as coarse bit transitions occur even at reset and signal conversion phases.
Innovation Solution
The method involves dynamically setting an offset value to prevent coarse bit transitions by maximizing the LSB DAC range, ensuring no coarse bit changes between reset and signal values up to the full scale of the fine section, and using an inverted reset conversion value during signal conversion to maintain consistent coarse bits, thereby minimizing DNL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a split-SAR architecture is used to make capacitor ratios more manageable in terms of area and layout, then device area is reduced, but differential non-linearity errors occur at coarse bit transitions
Solution Approach 1:
The patent applies preliminary action by performing a reset conversion before the signal conversion, and using the inverted reset conversion value to set the fine DAC during signal conversion. This preliminary reset operation establishes a baseline state that prevents coarse bit transitions during the subsequent signal conversion, thereby preventing DNL errors before they can occur during normal operation.
Solution Approach 2:
The patent changes the offset value parameter dynamically based on the inverted reset conversion value. By adjusting the fine DAC offset using the formula fine_DAC_offset = inverted_reset_fine_value + noise_offset, the system adapts the parameter to maintain consistent coarse bits during signal conversion, resolving the DNL issue while preserving the area benefits of the split architecture.
2Productivity
If coarse bit transitions occur during reset and signal conversion phases, then the converter operates continuously, but visual artifacts appear in the output image
Solution Approach 1:
The patent applies preliminary anti-action by using the inverted reset conversion value to preemptively counteract potential coarse bit transitions during signal conversion. By setting the fine DAC offset based on the inverted reset fine value, the system creates a compensating effect that prevents coarse bits from changing during the conversion phase, thereby eliminating the source of visual artifacts while maintaining continuous operation.
Solution Approach 2:
The patent implements feedback by using the reset conversion result to inform and adjust the signal conversion process. The inverted reset conversion value is fed back to set the fine DAC offset during signal conversion, creating a closed-loop mechanism that ensures coarse bits remain consistent and prevents artifacts from appearing in the output.
3Ease of manufacture
If the gain ratio of coarse and fine sections depends on parasitic capacitance, then layout flexibility is improved, but DNL error increases
Solution Approach 1:
The patent extracts the source of DNL error by isolating the parasitic capacitance effect to only the fine DAC section. By designing the coarse DAC without significant parasitic capacitance dependencies and using the inverted reset technique, the system separates the problematic parasitic effects from the critical gain ratio determination, allowing layout flexibility while maintaining precision.
Data Source
AI summary
An image sensor may contain an array of imaging pixels arranged in rows and columns. Each column of imaging pixels may be coupled to an analog-to-digital converter for converting analog imaging signals from the pixels to digital signals. The analog-to-digital converter may be implemented as a split successive approximation register (SAR) analog-to-digital converter (ADC). The split SAR ADC may include a coarse section and a fine section. During a reset sampling phase, a reset level is sampled with a predetermined pedestal value is applied to the coarse and fine sections. During reset conversion, a reset code is obtained. During a signal sampling phase, a signal level is sampled using inverted bits of the reset code for only the fine section. During signal conversion, a signal code is obtained. Operated in this way, differential non-linearity of the ADC is minimized.