Split SAR ADC Reference Settling for High-Bandwidth Image Sensors
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Solution Overview
Problem
Conventional image sensors with large arrays face slow reference settling and limited bandwidth due to typical analog-to-digital converters requiring a single reference voltage for capacitive digital-to-analog conversion, which restricts conversion time and efficiency.
Innovation Solution
Implementing a split SAR DAC with a coarse reference voltage for high slew rate and a fine reference voltage for accurate settling, allowing the coarse reference to be used in both the most significant and least significant bit banks, with the fine reference providing the final setting, thereby supporting high bandwidth and varying capacitive loads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single reference voltage is used in conventional analog-to-digital converters, then the design is simplified, but the reference settling speed decreases and bandwidth is limited
Solution Approach 1:
The patent divides the single reference voltage system into two separate reference voltages: a coarse reference voltage and a fine reference voltage. The coarse reference voltage is used during the initial settling phase to provide high slew rate, while the fine reference voltage is used for the final accurate settling. This segmentation allows each reference voltage to be optimized for its specific function, resolving the contradiction between design simplicity and settling speed.
Solution Approach 2:
The coarse reference voltage performs the preliminary action of rapid voltage settling before the fine reference voltage takes over for precise final settling. By performing the bulk of the settling work first with the coarse reference, the system achieves faster overall settling time while maintaining accuracy in the final stage.
2Device complexity
If a single reference voltage is used for every bit iteration, then the circuit structure is simplified, but the conversion time increases and bandwidth is limited
Solution Approach 1:
The conversion process is segmented into two phases: a first conversion phase using the coarse reference voltage for rapid initial conversion, and a second conversion phase using the fine reference voltage for precise final conversion. This time-based segmentation reduces the total conversion time by optimizing each phase for its specific requirement.
Solution Approach 2:
The patent implements periodic switching between coarse and fine reference voltages during the conversion process. The coarse reference is used initially, then switched to the fine reference for the remaining bits, creating a periodic action pattern that optimizes both speed and accuracy across the conversion cycle.
3Ease of manufacture
If a typical reference buffer is used, then the circuit implementation is straightforward, but the slew rate is limited and bandwidth is constrained
Solution Approach 1:
Different reference buffers are assigned to different reference voltages based on their specific requirements. The coarse reference buffer is designed with high slew rate capability to support rapid voltage changes, while the fine reference buffer is designed with high precision to support accurate final settling. This local quality optimization allows each buffer to be tailored to its specific function, improving overall system performance.
Data Source
AI summary
An imaging system may include an image sensor. The image sensor may have an array of image pixels arranged in rows and columns. Each column of image pixels may be coupled to column readout circuitry via a corresponding column line. The column readout circuitry may include analog-to-digital conversion circuitry. The analog-to-digital conversion circuitry may include split MSB and LSB capacitor banks. The MSB capacitor bank may include capacitors selectively coupled to a coarse reference voltage or a fine reference voltage. The LSB capacitor bank may include capacitors electively coupled to the coarse reference voltage.