Split-Capacitor SAR ADC Threshold Calibration for LSB Weight Estimation
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Solution Overview
Problem
Conventional split capacitor SAR ADCs are difficult to calibrate due to the non-functionality of the Least Significant Bit (LSB) weight in comparator decisions, making it challenging to estimate the LSB weight, which is crucial for pipeline ADCs.
Innovation Solution
A novel SAR ADC architecture with a calibration scheme that involves n+1 calibration measurements to determine the weights of sampling cells for each bit, allowing for facilitated estimation of the LSB weight by controlling switch circuits to adjust decision thresholds and detect threshold crossings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional split capacitor SAR ADC architecture is used, then analog implementation advantages are achieved, but calibration difficulty increases due to inability to estimate LSB weight
Solution Approach 1:
The patent performs calibration measurements before normal ADC operation to determine the actual weights of capacitor arrays. By conducting n+1 calibration measurements in advance, the system establishes reference weight values that are stored and used during subsequent conversions, eliminating the need for real-time calibration and resolving the contradiction between manufacturing simplicity and calibration ease
Solution Approach 2:
The patent introduces an intermediary calibration process that uses known test signals and comparator decision feedback to indirectly determine capacitor weights. This intermediary measurement system acts as a bridge between the fixed capacitor architecture and the required weight information, enabling calibration without modifying the fundamental split capacitor structure
2Device complexity
If conventional split capacitor SAR ADC is used, then architecture simplicity is maintained, but measurement precision of LSB weight deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where comparator decisions from calibration measurements are used to iteratively refine the estimated LSB weight. The system feeds back the comparison results to adjust weight estimates until convergence is achieved, thereby improving measurement precision while maintaining the simple split capacitor architecture
Solution Approach 2:
The patent performs n+1 calibration measurements, which is more than the minimum n measurements needed for basic functionality. This excessive action provides redundant data that improves the precision of LSB weight estimation through statistical averaging and error reduction, while the additional measurements are conducted offline without increasing operational complexity
Data Source
AI summary
A n-bit Successive Approximation Register Analog-to-Digital Converter, SAR ADC, is provided. The SAR ADC comprises a respective plurality of sampling cells for each bit of the n-bit of the SAR ADC. Each sampling cell comprises a capacitive element coupled to a cell output of the sampling cell in order to provide a cell output signal. Further, each sampling cell comprises a first cell input for receiving a first signal, and a first switch circuit capable of selectively coupling the first cell input to the capacitive element. Each cell additionally comprises a second cell input for receiving a second signal, and a third cell input for receiving a third signal. The third signal exhibits opposite polarity compared to the second signal. Each sampling cell comprises a second switch circuit capable of selectively coupling one of the second cell input and the third cell input to the capacitive element. The SAR ADC further comprises at least one comparator circuit coupled to the sampling cells. The at least one comparator circuit is configured to output a comparison signal based on the cell output signals of the sampling cells. Additionally, the SAR ADC comprises a calibration circuit configured to supply at least one respective control signal to the respective second switch circuit of the sampling cells for controlling the second switch circuits.