Peripheral Register Access with Split-Security Bus States
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Solution Overview
Problem
Existing integrated-circuit devices face inefficiencies in securing access to peripherals due to the need for separate secure and non-secure instances, increasing complexity and cost while existing hardware mechanisms are not granular enough to provide fine control over access to specific registers.
Innovation Solution
Implementing a peripheral component with a split-security state that allows secure and non-secure bus transactions to access different hardware registers, enabling finer granularity in security protection within the peripheral itself, rather than relying solely on upstream bus filtering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate secure and non-secure instances of the same peripheral are provided, then maximum functionality and security are achieved, but device complexity and cost increase
Solution Approach 1:
The peripheral is segmented into multiple register blocks, where each block can have independent security attributes. This allows different parts of the peripheral to have different security requirements, enabling a single peripheral instance to serve both secure and non-secure worlds without needing duplicate instances.
Solution Approach 2:
Different register blocks within the same peripheral are assigned different security qualities (secure or non-secure). This local differentiation allows the peripheral to provide targeted security protection only where needed, rather than applying security uniformly across the entire peripheral or requiring separate instances.
2Reliability
If hardware mechanisms are used to restrict access to secure resources, then security is improved, but access control granularity is insufficient
Solution Approach 1:
The peripheral's register interface is segmented into multiple register blocks that can be independently secured. This segmentation enables fine-grained access control at the register block level, allowing the system to protect only specific sensitive functions while leaving other functions accessible to non-secure code.
Solution Approach 2:
The patent introduces a new dimension of security control by adding security attributes to individual register blocks within a peripheral. This creates a hierarchical security model where security can be applied at the peripheral level, register block level, or individual register level, providing much finer granularity than traditional all-or-nothing peripheral security.
Data Source
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AI summary
An integrated-circuit device (1) comprises a processor(4), a peripheral component (12, 14, 16, 17), a bus system (2), connected to the processor (4) and to the peripheral component (12, 14, 16, 17), and configured to carry bus transactions; and hardware filter logic (24, 26). The bus system (2) is configured to carry security-state signals for distinguishing between secure and non-secure bus transactions. The peripheral component (12, 14, 16, 17) comprises a register interface (300, 400, 600), accessible over the bus system(2), and comprising a hardware register and a direct-memory- access (DMA) controller for initiating bus transactions on the bus system(2). The peripheral component (12, 14, 16, 17) supports a secure-in-and-non-secure-out state in which the hardware filter logic (24, 26) is configured to prevent non-secure bus transactions from accessing the hardware register of the peripheral component, but to allow secure bus transactions to access the peripheral component(12, 14, 16, 17). The peripheral component (12, 14, 16, 17) is configured to allow an incoming secure bus transaction to access the hardware register and to initiate a bus transaction as non-secure.