Split Slot FET with Embedded Drain for Miniaturization
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Solution Overview
Problem
Conventional MOSFETs face challenges in size reduction due to their lateral structure, which limits miniaturization and can affect performance, making it difficult to create compact transistors without compromising computing speed.
Innovation Solution
A field effect transistor (FET) with a vertical channel region is designed, featuring epitaxial layers, conductive layers, oxide layers, and nitride layers, with a 90-degree rotation of the channel region and a self-aligned poly-silicon drain, allowing for reduced surface area and increased voltage handling without lateral expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a lateral MOSFET structure is used, then the device has been in use for many years with established manufacturing processes, but the device size cannot be reduced beyond a certain limit and performance is affected
Solution Approach 1:
The patent transitions from a lateral MOSFET structure to a vertical FET structure by rotating the channel region 90 degrees. The channel is now formed vertically between source and drain regions, with the gate wrapping around the channel in a split-slot configuration. This dimensional change from lateral to vertical allows significant reduction in device footprint while maintaining or improving performance characteristics.
2Area of stationary object
If the transistor size is reduced to minimize device footprint, then the surface area is decreased, but the performance and computing speed are compromised
Solution Approach 1:
By implementing a vertical channel structure instead of lateral, the patent achieves high cell density and miniaturization without sacrificing performance. The vertical orientation allows the channel to extend deeper into the substrate, providing sufficient conduction path length for high-speed operation while minimizing the surface area occupied by each transistor.
Solution Approach 2:
The gate structure is wrapped around the channel in a split-slot configuration, with conductive layers positioned on opposite sidewalls of the channel. This nested arrangement allows the gate to control the channel from multiple directions, enhancing control efficiency and enabling smaller device dimensions while maintaining effective gate control for high-speed switching.
3Area of stationary object
If a vertical channel structure is implemented with 90-degree rotation, then the surface area is reduced and miniaturization is achieved, but the device complexity increases with multiple trenches and layers
Solution Approach 1:
The gate is divided into two separate conductive layers positioned on opposite sidewalls of the vertical channel, forming a split-slot structure. This segmentation allows each gate layer to independently control portions of the channel, providing effective electrostatic control while enabling a compact vertical layout that reduces surface area.
Solution Approach 2:
The gate conductive layers are nested within trenches formed in the semiconductor substrate, with oxide and nitride layers providing insulation and structural support. The vertical channel is nested within the split gate structure, creating a compact three-dimensional arrangement that minimizes footprint while managing structural complexity through organized layering.
Data Source
AI summary
The present invention provides an FET which includes an epitaxial layer and first and second body regions formed over the epitaxial layer. Further, the FET includes a first trench formed in the epitaxial layer between the first and the second body regions. The FET also includes a conductive layer formed on the sidewall of the first trench. The conductive layer acts as gate of the FET. The FET also includes a second trench formed at the bottom of the first trench, a first dielectric layer formed over the conductive layer and on the sidewall of the second trench, and a second dielectric layer formed on the first dielectric layer. Further, the FET includes a conductive layer, which acts as drain, deposited in the first and the second trenches. The FET also includes first and a second source regions formed in the first and second body regions, respectively.