Split Standard Cell Layout for Higher Yield and Active Region Area
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Solution Overview
Problem
The manufacturing of miniaturized semiconductor devices faces challenges such as high yield loss, reduced reliability of electrical interconnection, and low testing coverage due to increased complexity, necessitating improvements in device robustness and manufacturing efficiency.
Innovation Solution
The introduction of split-type standard cells with enlarged active regions, achieved by joining adjacent active regions through interconnection wiring, reduces the need for additional interconnection wiring and enhances performance by increasing the area of active regions, thereby improving device speed and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If standard cells are miniaturized to increase functional density, then the number of interconnected devices per chip area increases, but manufacturing complexity increases causing high yield loss and reduced reliability
Solution Approach 1:
The standard cell is divided into multiple segments along the column direction, with each segment containing a portion of the active region. This segmentation allows the active region to be distributed across multiple rows while maintaining the same cell height, thereby reducing the width of the active region and the number of interconnections required, which decreases manufacturing complexity and improves yield without sacrificing functional density.
2Area of stationary object
If standard cell size is reduced to increase chip area utilization, then more cells fit per chip area, but the area of active regions decreases impacting device performance
Solution Approach 1:
The active region is extended in the row direction across multiple rows while the cell height (column direction) remains constrained. This dimensional redistribution allows the active region to maintain sufficient area for device performance while the cell occupies less horizontal space, enabling higher chip area utilization without compromising active region quality.
3Adaptability or versatility
If additional interconnection wiring is added to connect active regions, then device functionality is improved, but manufacturing complexity and processing time increase
Solution Approach 1:
Adjacent active region portions from different segments are merged horizontally to form a continuous or closely-spaced active region structure. This merging reduces the need for additional interconnection wiring between segments, as the active regions are already positioned in close proximity, thereby maintaining device functionality while reducing interconnection complexity and processing time.
Data Source
AI summary
A semiconductor device includes a first power rail configured to supply a first voltage, a second power rail configured to supply a second voltage different from the first voltage, and a first cell arranged in a first row between the first and second power rails. The first cell has a first first-type active region and a first second-type active region. The semiconductor device further includes a second cell having a second first-type active region and a second second-type active region, wherein the second first-type active region extends in a second row and a third row on a first side of the first row. The semiconductor device also includes a third cell including a first portion and a second portion, wherein the first portion and the second portion are arranged on two sides of the first cell.