Split-Terminated Memory Signal Lines Without Separate VTT
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Solution Overview
Problem
Memory systems with multiple memory devices sharing command/address signal lines face increased costs due to the need for separate termination voltages, which modify the effective impedance and require additional voltage regulators.
Innovation Solution
Implementing a split-termination configuration using external impedance coupled to VDD and adjustable internal impedance, allowing for balanced or unbalanced termination without separate termination voltages, reducing power consumption and eliminating the need for additional termination control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate termination voltages are applied to external termination impedance, then signal communication reliability is improved, but system cost increases due to additional voltage regulators
Solution Approach 1:
The patent combines the termination function with existing power supply voltage rails (VDD/VSS) by implementing on-die termination (ODT) within the memory controller. Instead of using separate termination voltages requiring additional regulators, the termination impedance is integrated into the controller's power supply network, merging multiple functions into existing infrastructure and eliminating redundant components.
Solution Approach 2:
The memory controller performs its own termination function through internal impedance matching circuits that use the same power supply voltages already present for operational circuits. This self-service approach eliminates the need for external termination voltage generators, reducing system complexity while maintaining signal integrity through internally managed impedance control.
2Reliability
If separate termination voltages are used, then effective impedance control is improved, but power consumption increases
Solution Approach 1:
The termination function is merged with the existing power supply distribution network. The same VDD and VSS rails that power operational circuits are also used to bias the termination impedance, eliminating the need for separate termination voltage generation and reducing overall power consumption while maintaining effective impedance control.
Solution Approach 2:
The termination circuits are powered and controlled by the memory controller using its existing power supply infrastructure. This self-service power management eliminates redundant power consumption associated with separate termination voltage regulators, while the controller dynamically manages termination impedance to maintain signal integrity.
3Productivity
If multiple memory devices share signal lines in parallel, then system integration is improved, but impedance matching becomes more difficult
Solution Approach 1:
The patent implements local impedance matching at each memory device interface through on-die termination. Each device interface has its own termination impedance controlled by the memory controller, allowing localized impedance control that compensates for variations caused by parallel connections and trace variations, simplifying overall system impedance management.
Solution Approach 2:
The termination impedance is made dynamically controllable through programmable impedance settings in the memory controller. This allows the termination characteristics to be adjusted based on the specific configuration of memory devices and signal line conditions, enabling adaptive impedance matching that simplifies integration of multiple devices with varying electrical characteristics.
Data Source
AI summary
Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.