Split Transfer Gate Device for CMOS Image Sensor Charge Control

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Solution Overview

Problem

Current CMOS image sensors face challenges with image lag due to incomplete charge transfer from the photodiode to the floating node, as well as high dark current leakage, particularly when the transfer gate is turned off, leading to 'spillback' of charges into the photodiode.

Innovation Solution

A CMOS active pixel sensor (APS) cell structure with a transfer gate device featuring a gate dielectric layer and a gate conductor layer with separate n and p-type doped regions, allowing for a two-phase voltage bias to be applied, preventing charge spillback and enabling efficient charge transfer without 'spillback' into the photodiode.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a transfer gate is used to transfer charge from photodiode to floating diffusion, then charge transfer capability is improved, but charge spillback into photodiode occurs when transfer gate is turned off

Engineering Contradiction:
Improvecharge transfer capabilityVSAvoidcharge spillback
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The transfer gate is divided into two separate gates: a first transfer gate (n-type polysilicon) and a second transfer gate (p-type polysilicon). This segmentation allows independent control of charge transfer and spillback prevention, with each gate performing a specific function in the charge transfer process.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the transfer gate structure are doped with different conductivity types (n-type and p-type). The n-type region is optimized for efficient charge transfer from photodiode, while the p-type region provides potential barrier to prevent spillback, creating local quality variations that address different functional requirements.

Inventive Principle:
Principle #3Local quality

2Speed

If transfer gate voltage is increased to improve charge transfer efficiency, then charge transfer speed is improved, but dark current leakage increases

Engineering Contradiction:
Improvecharge transfer speedVSAvoiddark current leakage
Core Design Contradiction:
SpeedVSObject-generated harmful factors

Solution Approach 1:

The transfer gate operates with dynamically adjusted voltages on the first and second gates. During charge transfer, the first gate is biased to enable efficient transfer. During reset and storage phases, the second gate voltage is adjusted to create appropriate potential barriers, dynamically adapting to different operational phases to prevent dark current while maintaining transfer speed.

Inventive Principle:
Principle #15Dynamics

3Device complexity

If single gate structure is used, then device complexity is reduced, but ability to prevent charge spillback is insufficient

Engineering Contradiction:
Improvegate structure complexityVSAvoidspillback prevention capability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The transfer gate is divided into two separate gates: a first transfer gate (n-type polysilicon) and a second transfer gate (p-type polysilicon). This segmentation allows independent control of charge transfer and spillback prevention, with each gate performing a specific function in the charge transfer process.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first and second transfer gates have asymmetric doping types (n-type and p-type respectively) and are controlled by different voltage phases. This asymmetry enables differentiated functionality where one gate primarily handles charge transfer while the other provides spillback prevention, optimizing performance for each function.

Inventive Principle:
Principle #4Asymmetry

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces image lag and dark current leakage, allowing for accurate charge transfer from the photodiode to the diffusion region without 'spillback', thereby improving the overall performance of CMOS image sensors.

Implementation Method 1

a photosensing device formed at or below a substrate surface adjacent the first doped region of the gate conductor structure for collecting charge carriers in response to light incident thereto

Methodology Applied
Scientific EffectPhotoelectric effect: Photoelectric Effect

Implementation Method 2

the gate conductor layer defining a channel region enabling charge transfer between the photosensing device and the diffusion region

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS8227844B2Low lag transfer gate device
Publication Date: 2012.07.24 GLOBALFOUNDRIES US INC
  • US8227844B2 patent drawing
  • US8227844B2 patent drawing
  • US8227844B2 patent drawing

AI summary

A CMOS active pixel sensor (APS) cell structure includes at least one transfer gate device and method of operation. A first transfer gate device comprises a diodic or split transfer gate conductor structure having a first doped region of first conductivity type material and a second doped region of a second conductivity type material. A photosensing device is formed adjacent the first doped region for collecting charge carriers in response to light incident thereto, and, a diffusion region of a second conductivity type material is formed at or below the substrate surface adjacent the second doped region of the transfer gate device for receiving charges transferred from the photosensing device while preventing spillback of charges to the photosensing device upon timed voltage bias to the diodic or split transfer gate conductor structure.