Split Source-Drain Transistor Geometry for Stronger PUF Signatures

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Solution Overview

Problem

Physical unclonable function (PUF) circuits rely on transistors with limited manufacturing variations, making it difficult to generate a unique and detectable signature due to inherent electrical noise, requiring a large number of transistors to achieve a suitable signal.

Innovation Solution

Implementing a split source and drain configuration with unique geometries, such as inflection segments, to increase manufacturing variability and enhance signal differences between transistors, thereby amplifying the unique signature for security and authentication purposes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If transistors with flat uniform channels are used, then manufacturing is simple, but manufacturing variability is insufficient to generate detectable unique signatures

Engineering Contradiction:
Improvemanufacturing variabilityVSAvoidtransistor geometry complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The source and drain regions are segmented into multiple sub-regions with different geometries. The source region includes multiple source sub-regions and the drain region includes multiple drain sub-regions, where each sub-region has a distinct geometry (e.g., different widths, lengths, or shapes). This segmentation increases manufacturing variability by introducing geometric differences that amplify process variations, enabling detectable unique signatures while maintaining a structured design approach.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The source and drain regions are designed with asymmetric geometries relative to each other and to the channel. The source region may have different dimensional characteristics compared to the drain region, creating inherent asymmetry that enhances sensitivity to manufacturing variations. This asymmetric design ensures that process variations produce detectable differences in transistor characteristics, generating reliable unique signatures for PUF applications.

Inventive Principle:
Principle #4Asymmetry

2Reliability

If a large quantity of transistors is placed in the PUF circuit, then a suitable signal for unique signature is achieved, but circuit size and complexity increase

Engineering Contradiction:
Improvesignal qualityVSAvoidcircuit area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

Instead of using many identical transistors, the invention employs a smaller number of transistors where each transistor possesses unique local geometric qualities. Each transistor's source and drain regions have specific dimensional characteristics (widths, lengths, shapes) that differ from other transistors. This local quality differentiation amplifies the signal from manufacturing variations in each individual transistor, allowing fewer transistors to collectively provide a robust unique signature signal.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The invention changes the geometric parameters of transistor source and drain regions to enhance manufacturing variability. By varying parameters such as source/drain width, length, and shape across different transistors, the signal from process variations is amplified. This parameter diversification allows each transistor to contribute a stronger unique signal, reducing the total number of transistors needed while maintaining or improving signal quality for PUF functionality.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11876057B1Split source drain transistor
Publication Date: 2024.01.16 HONEYWELL FEDERAL MANUFACTURING & TECHNOLOGIES LLC
  • US11876057B1 patent drawing
  • US11876057B1 patent drawing
  • US11876057B1 patent drawing

AI summary

Systems, methods, circuits, and devices for providing and using transistors in a physically unclonable function (PUF) circuit. The transistors comprise a split source drain configuration including one or more inflection segments that increase process variations between the transistors such that each transistor generates a unique output signal.