Split Via Layout for Sub-15 Nm Interconnect Overlay Control
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Solution Overview
Problem
The scaling of integrated circuit features to sub-15 nanometer nodes is hindered by variability in conventional fabrication processes, requiring new methodologies to optimize performance and extend technology nodes, particularly in the formation of vias and metal interconnects where lithographic limitations and overlay precision pose challenges.
Innovation Solution
The implementation of split via structures and differentiated conductive lines using advanced patterning techniques such as pitch quartering and grating-based approaches, along with the use of materials like Co, Ru, W, or Mo for initial metallization, followed by backfilling with Cu, to enhance precision and scalability of metal lines and vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used, then manufacturing simplicity is maintained, but manufacturing precision deteriorates at sub-15 nanometer nodes
Solution Approach 1:
The patent applies segmentation by dividing a single via formation process into multiple stages: forming mandrels at a first pitch, depositing spacers, selectively removing portions, and forming final vias at a quartered pitch. This multi-step segmentation enables precise sub-15 nanometer via dimensions that cannot be achieved with conventional single-step lithography, directly resolving the contradiction between manufacturing precision and process complexity.
Solution Approach 2:
The patent utilizes the vertical dimension by forming three-dimensional structures including trenches extending through dielectric layers, vias penetrating multiple layers, and stacked metallization layers. This dimensional approach allows precise control of via dimensions and positions that cannot be achieved through planar lithography alone, enabling sub-15 nanometer precision while managing process complexity through vertical integration.
2Quantity of substance
If feature scaling continues, then device density increases, but lithographic limitations prevent further scaling
Solution Approach 1:
The patent employs self-aligned spacer formation where spacers are deposited conformally on mandrels and then etched back, automatically positioning features relative to each other without requiring additional lithographic alignment steps. This self-service mechanism enables quartered pitch features and high device density while overcoming lithographic resolution limits, as the spacer width is determined by deposition thickness rather than lithographic patterning.
3Measurement precision
If overlay precision is relaxed, then manufacturing complexity decreases, but via alignment accuracy deteriorates
Solution Approach 1:
The patent performs preliminary actions by forming mandrels and spacers with precise relative positions before final via formation. The spacer mandrel structure is established in advance with controlled dimensions and positioning, ensuring that subsequent via alignment is predetermined by the spacer geometry rather than requiring precise overlay during final patterning. This preliminary structuring achieves high via alignment accuracy while reducing overlay control complexity in later steps.
Data Source
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AI summary
Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a plurality of conductive lines in a first inter-layer dielectric (ILD) layer, the plurality of conductive lines on a same level and along a same direction. A second ILD layer is over the plurality of conductive lines and over the first ILD layer. A first conductive via is in a first opening in the second ILD layer, the first conductive via in contact with a first one of the plurality of conductive lines, the first conductive via having a straight edge. A second conductive via is in a second opening in the second ILD layer, the second conductive via in contact with a second one of the plurality of conductive lines, the second one of the plurality of conductive lines laterally spaced apart from the first one of the plurality of conductive lines, and the second conductive via having a straight edge, the straight edge of the second conductive via facing the straight edge of the first conductive via.