Split Conductive Via Layout for Tighter Semiconductor Spacing
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Solution Overview
Problem
Conventional Copper Dual-Damascene processes face challenges in maintaining efficient conductive via spacing and alignment as devices scale down, leading to inefficiencies and potential short-circuits, which traditional methods struggle to address.
Innovation Solution
A method involving the formation of conductive vias with sloped sidewalls and a self-aligning process using a hard mask to split conductive vias and lines, allowing for tighter spacing and improved electrical connections through a semi-damascene process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional Copper Dual-Damascene process is used, then conductive vias can be formed, but the via-to-via and trench-to-trench spacing becomes loose leading to space inefficiency and potential short-circuits
Solution Approach 1:
The patent applies segmentation by dividing a single conductive via into multiple split vias. The via is split into first and second conductive vias separated by a dielectric material, allowing tighter spacing while maintaining electrical isolation. This segmentation enables more efficient space utilization in the semiconductor layout while preventing short-circuits between adjacent structures.
Solution Approach 2:
The patent introduces a new dimensional aspect by adding vertical splitting of vias with dielectric material between the splits. Instead of only horizontal spacing, the via structure is divided in the vertical cross-section, creating a multi-dimensional approach to spacing that allows tighter center-to-center distances while maintaining electrical isolation through the dielectric layer.
2Manufacturing precision
If lithographic capabilities are used to define via spacing, then vias can be patterned, but the center-to-center spacing is limited restricting how closely vias can be placed
Solution Approach 1:
The patent applies preliminary action by forming the via structure with built-in splitting features before final patterning. The mandrel and dielectric layer are deposited and patterned in advance, creating a template that guides the subsequent via formation. This preliminary structuring enables tighter spacing by pre-defining the split via configuration, allowing the final lithography step to work within a more favorable geometry rather than attempting to directly pattern tightly spaced vias.
3Ease of manufacture
If traditional etching processes are used, then conductive vias can be formed, but alignment offsets and etching selectivity issues impact yield and performance
Solution Approach 1:
The patent introduces a dielectric material as an intermediary between the conductive via portions. This dielectric layer acts as a mediator that provides electrical isolation while allowing the via structures to be formed with tighter spacing. The intermediary dielectric material enables the etching process to create well-defined separated structures, improving alignment tolerance and reducing the impact of etching selectivity variations on final device performance.
Data Source
AI summary
The present disclosure relates to a method for forming an integrated circuit or an intermediate thereof. The method includes providing a second electrically conductive layer over a first electrically conductive line and in electrical contact with it, followed by etching the second layer to form a part of an electrically conductive via with a bottom surface, an exposed top surface smaller or equal to the bottom, and sidewalls. A third electrically conductive layer is then formed on the via, connecting the first line with the third layer. Subsequent etching through these layers forms a set of electrically conductive lines, splits the via, and interrupts the first line. This method provides the formation of electrical connections within an integrated circuit, which is useful for the performance and miniaturization of electronic devices.